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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>This header file contains the identifiers and low-level driver functions (or macros) that can be used to access the device. </p>
<p>High-level driver functions are defined in <a class="el" href="xdppsu_8h.html" title="The Xilinx DisplayPort transmitter (DPTX_PS) driver. ">xdppsu.h</a>.</p>
<dl class="section note"><dt>Note</dt><dd>None.</dd></dl>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who  Date     Changes
</p>
<hr/>
<p>
1.0   aad  23/01/17 Initial release.
1.1   aad  10/04/17 Removed un-applicable registers
</pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:a236d6b24b5cf2e0e8ac65a4079ae93bc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a236d6b24b5cf2e0e8ac65a4079ae93bc">XDpPsu_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;XDpPsu_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:a236d6b24b5cf2e0e8ac65a4079ae93bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is a low-level function that reads from the specified register.  <a href="#a236d6b24b5cf2e0e8ac65a4079ae93bc">More...</a><br/></td></tr>
<tr class="separator:a236d6b24b5cf2e0e8ac65a4079ae93bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a823328e4a95aa3ba27553603940a7ba8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a823328e4a95aa3ba27553603940a7ba8">XDpPsu_WriteReg</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;XDpPsu_Out32((BaseAddress) + (RegOffset), (Data))</td></tr>
<tr class="memdesc:a823328e4a95aa3ba27553603940a7ba8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is a low-level function that writes to the specified register.  <a href="#a823328e4a95aa3ba27553603940a7ba8">More...</a><br/></td></tr>
<tr class="separator:a823328e4a95aa3ba27553603940a7ba8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DPPSU core registers: Link configuration field.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Address mapping for the DisplayPort TX core. </p>
</div></td></tr>
<tr class="memitem:a39533d8f8e18fce7b13f84d440b6b176"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a39533d8f8e18fce7b13f84d440b6b176">XDPPSU_LINK_BW_SET</a>&#160;&#160;&#160;0x0000</td></tr>
<tr class="memdesc:a39533d8f8e18fce7b13f84d440b6b176"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set main link bandwidth setting.  <a href="#a39533d8f8e18fce7b13f84d440b6b176">More...</a><br/></td></tr>
<tr class="separator:a39533d8f8e18fce7b13f84d440b6b176"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a25090ba43a6682938a143310ed73d844"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a25090ba43a6682938a143310ed73d844">XDPPSU_LANE_COUNT_SET</a>&#160;&#160;&#160;0x0004</td></tr>
<tr class="memdesc:a25090ba43a6682938a143310ed73d844"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set lane count setting.  <a href="#a25090ba43a6682938a143310ed73d844">More...</a><br/></td></tr>
<tr class="separator:a25090ba43a6682938a143310ed73d844"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acb217703567249190f6250fba75a0a38"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#acb217703567249190f6250fba75a0a38">XDPPSU_ENHANCED_FRAME_EN</a>&#160;&#160;&#160;0x0008</td></tr>
<tr class="memdesc:acb217703567249190f6250fba75a0a38"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable enhanced framing symbol sequence.  <a href="#acb217703567249190f6250fba75a0a38">More...</a><br/></td></tr>
<tr class="separator:acb217703567249190f6250fba75a0a38"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa2d0f8311673ee64d8836b35d31c09ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#aa2d0f8311673ee64d8836b35d31c09ad">XDPPSU_TRAINING_PATTERN_SET</a>&#160;&#160;&#160;0x000C</td></tr>
<tr class="memdesc:aa2d0f8311673ee64d8836b35d31c09ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the link training pattern.  <a href="#aa2d0f8311673ee64d8836b35d31c09ad">More...</a><br/></td></tr>
<tr class="separator:aa2d0f8311673ee64d8836b35d31c09ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a637f77a0a0d58a0c55799c07ceb8fa62"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a637f77a0a0d58a0c55799c07ceb8fa62">XDPPSU_LINK_QUAL_PATTERN_SET</a>&#160;&#160;&#160;0x0010</td></tr>
<tr class="memdesc:a637f77a0a0d58a0c55799c07ceb8fa62"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit the link quality pattern.  <a href="#a637f77a0a0d58a0c55799c07ceb8fa62">More...</a><br/></td></tr>
<tr class="separator:a637f77a0a0d58a0c55799c07ceb8fa62"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6025e9ebba67eb43d4e7894386b0806e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a6025e9ebba67eb43d4e7894386b0806e">XDPPSU_SCRAMBLING_DISABLE</a>&#160;&#160;&#160;0x0014</td></tr>
<tr class="memdesc:a6025e9ebba67eb43d4e7894386b0806e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable scrambler and transmit all symbols.  <a href="#a6025e9ebba67eb43d4e7894386b0806e">More...</a><br/></td></tr>
<tr class="separator:a6025e9ebba67eb43d4e7894386b0806e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad4beaa963b7a63da99c8663caa7c7440"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ad4beaa963b7a63da99c8663caa7c7440">XDPPSU_DOWNSPREAD_CTRL</a>&#160;&#160;&#160;0x0018</td></tr>
<tr class="memdesc:ad4beaa963b7a63da99c8663caa7c7440"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable a 0.5% spreading of the clock.  <a href="#ad4beaa963b7a63da99c8663caa7c7440">More...</a><br/></td></tr>
<tr class="separator:ad4beaa963b7a63da99c8663caa7c7440"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a71f335fd19c1b8f3bc3eb9a3fbf4644c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a71f335fd19c1b8f3bc3eb9a3fbf4644c">XDPPSU_SOFT_RESET</a>&#160;&#160;&#160;0x001C</td></tr>
<tr class="memdesc:a71f335fd19c1b8f3bc3eb9a3fbf4644c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Software reset.  <a href="#a71f335fd19c1b8f3bc3eb9a3fbf4644c">More...</a><br/></td></tr>
<tr class="separator:a71f335fd19c1b8f3bc3eb9a3fbf4644c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DPPSU core registers: 80-bit custom patterns for link quality test.</div></td></tr>
<tr class="memitem:ae89c4c9be38f83e506638165ea64cc19"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ae89c4c9be38f83e506638165ea64cc19">XDPPSU_COMP_PATTERN_80BIT_1</a>&#160;&#160;&#160;0x0020</td></tr>
<tr class="memdesc:ae89c4c9be38f83e506638165ea64cc19"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bits [31:0] of the 80-bit custom pattern.  <a href="#ae89c4c9be38f83e506638165ea64cc19">More...</a><br/></td></tr>
<tr class="separator:ae89c4c9be38f83e506638165ea64cc19"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aaf7e198c14d1dcdba81756020c94ceaf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#aaf7e198c14d1dcdba81756020c94ceaf">XDPPSU_COMP_PATTERN_80BIT_2</a>&#160;&#160;&#160;0x0024</td></tr>
<tr class="memdesc:aaf7e198c14d1dcdba81756020c94ceaf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bits [63:32] of the 80-bit custom pattern.  <a href="#aaf7e198c14d1dcdba81756020c94ceaf">More...</a><br/></td></tr>
<tr class="separator:aaf7e198c14d1dcdba81756020c94ceaf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a427d39bb639fc7e4f1a7c4f04e712435"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a427d39bb639fc7e4f1a7c4f04e712435">XDPPSU_COMP_PATTERN_80BIT_3</a>&#160;&#160;&#160;0x0028</td></tr>
<tr class="memdesc:a427d39bb639fc7e4f1a7c4f04e712435"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bits [79:64] of the 80-bit custom pattern.  <a href="#a427d39bb639fc7e4f1a7c4f04e712435">More...</a><br/></td></tr>
<tr class="separator:a427d39bb639fc7e4f1a7c4f04e712435"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DPPSU core registers: Core enables.</div></td></tr>
<tr class="memitem:a18e71ddca3a5336d64bdf3a7ed75e3f9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a18e71ddca3a5336d64bdf3a7ed75e3f9">XDPPSU_ENABLE</a>&#160;&#160;&#160;0x0080</td></tr>
<tr class="memdesc:a18e71ddca3a5336d64bdf3a7ed75e3f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the basic operations of the DisplayPort TX core or output stuffing symbols if disabled.  <a href="#a18e71ddca3a5336d64bdf3a7ed75e3f9">More...</a><br/></td></tr>
<tr class="separator:a18e71ddca3a5336d64bdf3a7ed75e3f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a13298309408d465cf884b2b5eb78009b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a13298309408d465cf884b2b5eb78009b">XDPPSU_ENABLE_MAIN_STREAM</a>&#160;&#160;&#160;0x0084</td></tr>
<tr class="memdesc:a13298309408d465cf884b2b5eb78009b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable transmission of main link video info.  <a href="#a13298309408d465cf884b2b5eb78009b">More...</a><br/></td></tr>
<tr class="separator:a13298309408d465cf884b2b5eb78009b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa04733c4a40ad233e107c38c163a3423"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#aa04733c4a40ad233e107c38c163a3423">XDPPSU_FORCE_SCRAMBLER_RESET</a>&#160;&#160;&#160;0x00C0</td></tr>
<tr class="memdesc:aa04733c4a40ad233e107c38c163a3423"><td class="mdescLeft">&#160;</td><td class="mdescRight">Force a scrambler reset.  <a href="#aa04733c4a40ad233e107c38c163a3423">More...</a><br/></td></tr>
<tr class="separator:aa04733c4a40ad233e107c38c163a3423"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DPPSU core registers: Core ID.</div></td></tr>
<tr class="memitem:a24ceb9ccb9922017c077c8ec72fd3ad2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a24ceb9ccb9922017c077c8ec72fd3ad2">XDPPSU_VERSION</a>&#160;&#160;&#160;0x00F8</td></tr>
<tr class="memdesc:a24ceb9ccb9922017c077c8ec72fd3ad2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core version.  <a href="#a24ceb9ccb9922017c077c8ec72fd3ad2">More...</a><br/></td></tr>
<tr class="separator:a24ceb9ccb9922017c077c8ec72fd3ad2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a838e534d7fa83c991d92ea2816e54e9b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a838e534d7fa83c991d92ea2816e54e9b">XDPPSU_CORE_ID</a>&#160;&#160;&#160;0x00FC</td></tr>
<tr class="memdesc:a838e534d7fa83c991d92ea2816e54e9b"><td class="mdescLeft">&#160;</td><td class="mdescRight">DisplayPort revision.  <a href="#a838e534d7fa83c991d92ea2816e54e9b">More...</a><br/></td></tr>
<tr class="separator:a838e534d7fa83c991d92ea2816e54e9b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DPPSU core registers: AUX channel interface.</div></td></tr>
<tr class="memitem:a31902e97fbf794a6d9922965934a58e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a31902e97fbf794a6d9922965934a58e7">XDPPSU_AUX_CMD</a>&#160;&#160;&#160;0x0100</td></tr>
<tr class="memdesc:a31902e97fbf794a6d9922965934a58e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initiates AUX commands.  <a href="#a31902e97fbf794a6d9922965934a58e7">More...</a><br/></td></tr>
<tr class="separator:a31902e97fbf794a6d9922965934a58e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a491175e394de4ec51f460abb147d7a1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a491175e394de4ec51f460abb147d7a1f">XDPPSU_AUX_WRITE_FIFO</a>&#160;&#160;&#160;0x0104</td></tr>
<tr class="memdesc:a491175e394de4ec51f460abb147d7a1f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write data for the current AUX command.  <a href="#a491175e394de4ec51f460abb147d7a1f">More...</a><br/></td></tr>
<tr class="separator:a491175e394de4ec51f460abb147d7a1f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2106632c315d3ad5f685330476ca417c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a2106632c315d3ad5f685330476ca417c">XDPPSU_AUX_ADDRESS</a>&#160;&#160;&#160;0x0108</td></tr>
<tr class="memdesc:a2106632c315d3ad5f685330476ca417c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Specifies the address of current AUX command.  <a href="#a2106632c315d3ad5f685330476ca417c">More...</a><br/></td></tr>
<tr class="separator:a2106632c315d3ad5f685330476ca417c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aadb1a6ac37fc2e571c2a0c5ba90ece94"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#aadb1a6ac37fc2e571c2a0c5ba90ece94">XDPPSU_AUX_CLK_DIVIDER</a>&#160;&#160;&#160;0x010C</td></tr>
<tr class="memdesc:aadb1a6ac37fc2e571c2a0c5ba90ece94"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock divider value for generating the internal 1MHz clock.  <a href="#aadb1a6ac37fc2e571c2a0c5ba90ece94">More...</a><br/></td></tr>
<tr class="separator:aadb1a6ac37fc2e571c2a0c5ba90ece94"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6100fd7c2396d31135f5576668e244d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a6100fd7c2396d31135f5576668e244d3">XDPPSU_TX_USER_FIFO_OVERFLOW</a>&#160;&#160;&#160;0x0110</td></tr>
<tr class="memdesc:a6100fd7c2396d31135f5576668e244d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Indicates an overflow in user FIFO.  <a href="#a6100fd7c2396d31135f5576668e244d3">More...</a><br/></td></tr>
<tr class="separator:a6100fd7c2396d31135f5576668e244d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3f100eb641ca948e3ae71bb33b5e6512"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a3f100eb641ca948e3ae71bb33b5e6512">XDPPSU_INTERRUPT_SIG_STATE</a>&#160;&#160;&#160;0x0130</td></tr>
<tr class="memdesc:a3f100eb641ca948e3ae71bb33b5e6512"><td class="mdescLeft">&#160;</td><td class="mdescRight">The raw signal values for interupt events.  <a href="#a3f100eb641ca948e3ae71bb33b5e6512">More...</a><br/></td></tr>
<tr class="separator:a3f100eb641ca948e3ae71bb33b5e6512"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ace290d743c9b56c18e1fb8c8be942706"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ace290d743c9b56c18e1fb8c8be942706">XDPPSU_AUX_REPLY_DATA</a>&#160;&#160;&#160;0x0134</td></tr>
<tr class="memdesc:ace290d743c9b56c18e1fb8c8be942706"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reply data received during the AUX reply.  <a href="#ace290d743c9b56c18e1fb8c8be942706">More...</a><br/></td></tr>
<tr class="separator:ace290d743c9b56c18e1fb8c8be942706"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a826c4ff76f6051e55152b916147fdbd9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a826c4ff76f6051e55152b916147fdbd9">XDPPSU_AUX_REPLY_CODE</a>&#160;&#160;&#160;0x0138</td></tr>
<tr class="memdesc:a826c4ff76f6051e55152b916147fdbd9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reply code received from the most recent AUX command.  <a href="#a826c4ff76f6051e55152b916147fdbd9">More...</a><br/></td></tr>
<tr class="separator:a826c4ff76f6051e55152b916147fdbd9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7721ad9f0a05d04280627008ea3fdaa0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a7721ad9f0a05d04280627008ea3fdaa0">XDPPSU_AUX_REPLY_COUNT</a>&#160;&#160;&#160;0x013C</td></tr>
<tr class="memdesc:a7721ad9f0a05d04280627008ea3fdaa0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of reply transactions receieved over AUX.  <a href="#a7721ad9f0a05d04280627008ea3fdaa0">More...</a><br/></td></tr>
<tr class="separator:a7721ad9f0a05d04280627008ea3fdaa0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6290aae7acf47770b47ca197d0a0c6c9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a6290aae7acf47770b47ca197d0a0c6c9">XDPPSU_REPLY_DATA_COUNT</a>&#160;&#160;&#160;0x0148</td></tr>
<tr class="memdesc:a6290aae7acf47770b47ca197d0a0c6c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Total number of data bytes actually received during a transaction.  <a href="#a6290aae7acf47770b47ca197d0a0c6c9">More...</a><br/></td></tr>
<tr class="separator:a6290aae7acf47770b47ca197d0a0c6c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa9125d1e1b2dd161005e744f50514539"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#aa9125d1e1b2dd161005e744f50514539">XDPPSU_REPLY_STATUS</a>&#160;&#160;&#160;0x014C</td></tr>
<tr class="memdesc:aa9125d1e1b2dd161005e744f50514539"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reply status of most recent AUX transaction.  <a href="#aa9125d1e1b2dd161005e744f50514539">More...</a><br/></td></tr>
<tr class="separator:aa9125d1e1b2dd161005e744f50514539"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a728bb80efc84e6cb161e3f04103bf6ed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a728bb80efc84e6cb161e3f04103bf6ed">XDPPSU_HPD_DURATION</a>&#160;&#160;&#160;0x0150</td></tr>
<tr class="memdesc:a728bb80efc84e6cb161e3f04103bf6ed"><td class="mdescLeft">&#160;</td><td class="mdescRight">Duration of the HPD pulse in microseconds.  <a href="#a728bb80efc84e6cb161e3f04103bf6ed">More...</a><br/></td></tr>
<tr class="separator:a728bb80efc84e6cb161e3f04103bf6ed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DPPSU core registers: Main stream attributes.</div></td></tr>
<tr class="memitem:acfae349a9726fe324642e099ebbfb356"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#acfae349a9726fe324642e099ebbfb356">XDPPSU_MAIN_STREAM_HTOTAL</a>&#160;&#160;&#160;0x0180</td></tr>
<tr class="memdesc:acfae349a9726fe324642e099ebbfb356"><td class="mdescLeft">&#160;</td><td class="mdescRight">Total number of clocks in the horizontal framing period.  <a href="#acfae349a9726fe324642e099ebbfb356">More...</a><br/></td></tr>
<tr class="separator:acfae349a9726fe324642e099ebbfb356"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa4d7607e0a3dbca00150115881ecca65"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#aa4d7607e0a3dbca00150115881ecca65">XDPPSU_MAIN_STREAM_VTOTAL</a>&#160;&#160;&#160;0x0184</td></tr>
<tr class="memdesc:aa4d7607e0a3dbca00150115881ecca65"><td class="mdescLeft">&#160;</td><td class="mdescRight">Total number of lines in the video frame.  <a href="#aa4d7607e0a3dbca00150115881ecca65">More...</a><br/></td></tr>
<tr class="separator:aa4d7607e0a3dbca00150115881ecca65"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa7738c02d0883e7d17f1ab000af800de"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#aa7738c02d0883e7d17f1ab000af800de">XDPPSU_MAIN_STREAM_POLARITY</a>&#160;&#160;&#160;0x0188</td></tr>
<tr class="memdesc:aa7738c02d0883e7d17f1ab000af800de"><td class="mdescLeft">&#160;</td><td class="mdescRight">Polarity for the video sync signals.  <a href="#aa7738c02d0883e7d17f1ab000af800de">More...</a><br/></td></tr>
<tr class="separator:aa7738c02d0883e7d17f1ab000af800de"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a12ef125fc3c17f329374fb7082d91e81"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a12ef125fc3c17f329374fb7082d91e81">XDPPSU_MAIN_STREAM_HSWIDTH</a>&#160;&#160;&#160;0x018C</td></tr>
<tr class="memdesc:a12ef125fc3c17f329374fb7082d91e81"><td class="mdescLeft">&#160;</td><td class="mdescRight">Width of the horizontal sync pulse.  <a href="#a12ef125fc3c17f329374fb7082d91e81">More...</a><br/></td></tr>
<tr class="separator:a12ef125fc3c17f329374fb7082d91e81"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a89b4198d0838f5b13c3efc018bfff63e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a89b4198d0838f5b13c3efc018bfff63e">XDPPSU_MAIN_STREAM_VSWIDTH</a>&#160;&#160;&#160;0x0190</td></tr>
<tr class="memdesc:a89b4198d0838f5b13c3efc018bfff63e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Width of the vertical sync pulse.  <a href="#a89b4198d0838f5b13c3efc018bfff63e">More...</a><br/></td></tr>
<tr class="separator:a89b4198d0838f5b13c3efc018bfff63e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a27ba254de82f62941d184b8962dca6a9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a27ba254de82f62941d184b8962dca6a9">XDPPSU_MAIN_STREAM_HRES</a>&#160;&#160;&#160;0x0194</td></tr>
<tr class="memdesc:a27ba254de82f62941d184b8962dca6a9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of active pixels per line (the horizontal resolution).  <a href="#a27ba254de82f62941d184b8962dca6a9">More...</a><br/></td></tr>
<tr class="separator:a27ba254de82f62941d184b8962dca6a9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9d8763c359f1036ef3af7aabd92fc61b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a9d8763c359f1036ef3af7aabd92fc61b">XDPPSU_MAIN_STREAM_VRES</a>&#160;&#160;&#160;0x0198</td></tr>
<tr class="memdesc:a9d8763c359f1036ef3af7aabd92fc61b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of active lines (the vertical resolution).  <a href="#a9d8763c359f1036ef3af7aabd92fc61b">More...</a><br/></td></tr>
<tr class="separator:a9d8763c359f1036ef3af7aabd92fc61b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6515d0120b4a6fcd2769d651f9c85335"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a6515d0120b4a6fcd2769d651f9c85335">XDPPSU_MAIN_STREAM_HSTART</a>&#160;&#160;&#160;0x019C</td></tr>
<tr class="memdesc:a6515d0120b4a6fcd2769d651f9c85335"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of clocks between the leading edge of the horizontal sync and the start of active data.  <a href="#a6515d0120b4a6fcd2769d651f9c85335">More...</a><br/></td></tr>
<tr class="separator:a6515d0120b4a6fcd2769d651f9c85335"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adaccb873812cdd56a0a9400f525bccb0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#adaccb873812cdd56a0a9400f525bccb0">XDPPSU_MAIN_STREAM_VSTART</a>&#160;&#160;&#160;0x01A0</td></tr>
<tr class="memdesc:adaccb873812cdd56a0a9400f525bccb0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of lines between the leading edge of the vertical sync and the first line of active data.  <a href="#adaccb873812cdd56a0a9400f525bccb0">More...</a><br/></td></tr>
<tr class="separator:adaccb873812cdd56a0a9400f525bccb0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4c8b7aedd1df781e3ca81a9d54fd3e6a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a4c8b7aedd1df781e3ca81a9d54fd3e6a">XDPPSU_MAIN_STREAM_MISC0</a>&#160;&#160;&#160;0x01A4</td></tr>
<tr class="memdesc:a4c8b7aedd1df781e3ca81a9d54fd3e6a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Miscellaneous stream attributes.  <a href="#a4c8b7aedd1df781e3ca81a9d54fd3e6a">More...</a><br/></td></tr>
<tr class="separator:a4c8b7aedd1df781e3ca81a9d54fd3e6a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a68bdadc636b21a7130f9d6f2444b6908"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a68bdadc636b21a7130f9d6f2444b6908">XDPPSU_MAIN_STREAM_MISC1</a>&#160;&#160;&#160;0x01A8</td></tr>
<tr class="memdesc:a68bdadc636b21a7130f9d6f2444b6908"><td class="mdescLeft">&#160;</td><td class="mdescRight">Miscellaneous stream attributes.  <a href="#a68bdadc636b21a7130f9d6f2444b6908">More...</a><br/></td></tr>
<tr class="separator:a68bdadc636b21a7130f9d6f2444b6908"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae42d697245eb12b0caae5f2cdec459ed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ae42d697245eb12b0caae5f2cdec459ed">XDPPSU_M_VID</a>&#160;&#160;&#160;0x01AC</td></tr>
<tr class="memdesc:ae42d697245eb12b0caae5f2cdec459ed"><td class="mdescLeft">&#160;</td><td class="mdescRight">M value for the video stream as computed by the source core in asynchronous clock mode.  <a href="#ae42d697245eb12b0caae5f2cdec459ed">More...</a><br/></td></tr>
<tr class="separator:ae42d697245eb12b0caae5f2cdec459ed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a842268c74f2d73c00df473e71fb54b86"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a842268c74f2d73c00df473e71fb54b86">XDPPSU_TU_SIZE</a>&#160;&#160;&#160;0x01B0</td></tr>
<tr class="memdesc:a842268c74f2d73c00df473e71fb54b86"><td class="mdescLeft">&#160;</td><td class="mdescRight">Size of a transfer unit in the framing logic.  <a href="#a842268c74f2d73c00df473e71fb54b86">More...</a><br/></td></tr>
<tr class="separator:a842268c74f2d73c00df473e71fb54b86"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a402b43e835fbfff366b961880262d3ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a402b43e835fbfff366b961880262d3ba">XDPPSU_N_VID</a>&#160;&#160;&#160;0x01B4</td></tr>
<tr class="memdesc:a402b43e835fbfff366b961880262d3ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">N value for the video stream as computed by the source core in asynchronous clock mode.  <a href="#a402b43e835fbfff366b961880262d3ba">More...</a><br/></td></tr>
<tr class="separator:a402b43e835fbfff366b961880262d3ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa9be13696d4f6db43e903d239a61dd2b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#aa9be13696d4f6db43e903d239a61dd2b">XDPPSU_USER_PIXEL_WIDTH</a>&#160;&#160;&#160;0x01B8</td></tr>
<tr class="memdesc:aa9be13696d4f6db43e903d239a61dd2b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Selects the width of the user data input port.  <a href="#aa9be13696d4f6db43e903d239a61dd2b">More...</a><br/></td></tr>
<tr class="separator:aa9be13696d4f6db43e903d239a61dd2b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a30a942297a72b501359f4818da8e5515"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a30a942297a72b501359f4818da8e5515">XDPPSU_USER_DATA_COUNT_PER_LANE</a>&#160;&#160;&#160;0x01BC</td></tr>
<tr class="memdesc:a30a942297a72b501359f4818da8e5515"><td class="mdescLeft">&#160;</td><td class="mdescRight">Used to translate the number of pixels per line to the native internal 16-bit datapath.  <a href="#a30a942297a72b501359f4818da8e5515">More...</a><br/></td></tr>
<tr class="separator:a30a942297a72b501359f4818da8e5515"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae809ab48c87900a9b2cd219d8385f3d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ae809ab48c87900a9b2cd219d8385f3d5">XDPPSU_MIN_BYTES_PER_TU</a>&#160;&#160;&#160;0x01C4</td></tr>
<tr class="memdesc:ae809ab48c87900a9b2cd219d8385f3d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">The minimum number of bytes per transfer unit.  <a href="#ae809ab48c87900a9b2cd219d8385f3d5">More...</a><br/></td></tr>
<tr class="separator:ae809ab48c87900a9b2cd219d8385f3d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2221a5ada815d383adda40c0badcb74d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a2221a5ada815d383adda40c0badcb74d">XDPPSU_FRAC_BYTES_PER_TU</a>&#160;&#160;&#160;0x01C8</td></tr>
<tr class="memdesc:a2221a5ada815d383adda40c0badcb74d"><td class="mdescLeft">&#160;</td><td class="mdescRight">The fractional component when calculated the XDPPSU_MIN_BYTES_PER_TU register value.  <a href="#a2221a5ada815d383adda40c0badcb74d">More...</a><br/></td></tr>
<tr class="separator:a2221a5ada815d383adda40c0badcb74d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac1bfc95808e680c14095348df796eff3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ac1bfc95808e680c14095348df796eff3">XDPPSU_INIT_WAIT</a>&#160;&#160;&#160;0x01CC</td></tr>
<tr class="memdesc:ac1bfc95808e680c14095348df796eff3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO.  <a href="#ac1bfc95808e680c14095348df796eff3">More...</a><br/></td></tr>
<tr class="separator:ac1bfc95808e680c14095348df796eff3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DPPSU core registers: PHY configuration status.</div></td></tr>
<tr class="memitem:ad564b6d94b00f66d20f2469f924a0a19"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ad564b6d94b00f66d20f2469f924a0a19">XDPPSU_PHY_CONFIG</a>&#160;&#160;&#160;0x0200</td></tr>
<tr class="memdesc:ad564b6d94b00f66d20f2469f924a0a19"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transceiver PHY reset and configuration.  <a href="#ad564b6d94b00f66d20f2469f924a0a19">More...</a><br/></td></tr>
<tr class="separator:ad564b6d94b00f66d20f2469f924a0a19"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad4d20e2d6ab1c2d9d4cd8ef7e1f6e04a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ad4d20e2d6ab1c2d9d4cd8ef7e1f6e04a">XDPPSU_PHY_TRANSMIT_PRBS7</a>&#160;&#160;&#160;0x0230</td></tr>
<tr class="memdesc:ad4d20e2d6ab1c2d9d4cd8ef7e1f6e04a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable pseudo random bit sequence 7 pattern transmission for link quality assessment.  <a href="#ad4d20e2d6ab1c2d9d4cd8ef7e1f6e04a">More...</a><br/></td></tr>
<tr class="separator:ad4d20e2d6ab1c2d9d4cd8ef7e1f6e04a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a35f964035ad6eade3df5b8539989b536"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a35f964035ad6eade3df5b8539989b536">XDPPSU_PHY_CLOCK_SELECT</a>&#160;&#160;&#160;0x0234</td></tr>
<tr class="memdesc:a35f964035ad6eade3df5b8539989b536"><td class="mdescLeft">&#160;</td><td class="mdescRight">Instructs the PHY PLL to generate the proper clock frequency for the required link rate.  <a href="#a35f964035ad6eade3df5b8539989b536">More...</a><br/></td></tr>
<tr class="separator:a35f964035ad6eade3df5b8539989b536"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a14ddf17f3094011de0f16a11d86bbc63"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a14ddf17f3094011de0f16a11d86bbc63">XDPPSU_TX_PHY_POWER_DOWN</a>&#160;&#160;&#160;0x0238</td></tr>
<tr class="memdesc:a14ddf17f3094011de0f16a11d86bbc63"><td class="mdescLeft">&#160;</td><td class="mdescRight">Controls PHY power down.  <a href="#a14ddf17f3094011de0f16a11d86bbc63">More...</a><br/></td></tr>
<tr class="separator:a14ddf17f3094011de0f16a11d86bbc63"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afd27646d6bf849e2605ec977e0906bb0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#afd27646d6bf849e2605ec977e0906bb0">XDPPSU_PHY_PRECURSOR_LANE_0</a>&#160;&#160;&#160;0x024C</td></tr>
<tr class="memdesc:afd27646d6bf849e2605ec977e0906bb0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Controls the pre-cursor level.  <a href="#afd27646d6bf849e2605ec977e0906bb0">More...</a><br/></td></tr>
<tr class="separator:afd27646d6bf849e2605ec977e0906bb0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6b8dfc6e98b73a331306b25535d484bb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a6b8dfc6e98b73a331306b25535d484bb">XDPPSU_PHY_PRECURSOR_LANE_1</a>&#160;&#160;&#160;0x0250</td></tr>
<tr class="memdesc:a6b8dfc6e98b73a331306b25535d484bb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Controls the pre-cursor level.  <a href="#a6b8dfc6e98b73a331306b25535d484bb">More...</a><br/></td></tr>
<tr class="separator:a6b8dfc6e98b73a331306b25535d484bb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8d13e1e98899a0d08dff3fe38f252f3a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a8d13e1e98899a0d08dff3fe38f252f3a">XDPPSU_PHY_STATUS</a>&#160;&#160;&#160;0x0280</td></tr>
<tr class="memdesc:a8d13e1e98899a0d08dff3fe38f252f3a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Current PHY status.  <a href="#a8d13e1e98899a0d08dff3fe38f252f3a">More...</a><br/></td></tr>
<tr class="separator:a8d13e1e98899a0d08dff3fe38f252f3a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DPPSU core registers: DisplayPort audio.</div></td></tr>
<tr class="memitem:a2a830ba69a1227e5e0c81723ac207564"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a2a830ba69a1227e5e0c81723ac207564">XDPPSU_TX_AUDIO_CONTROL</a>&#160;&#160;&#160;0x0300</td></tr>
<tr class="memdesc:a2a830ba69a1227e5e0c81723ac207564"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables audio stream packets in main link and buffer control.  <a href="#a2a830ba69a1227e5e0c81723ac207564">More...</a><br/></td></tr>
<tr class="separator:a2a830ba69a1227e5e0c81723ac207564"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a72f3966bc5404d485e40130efefe701e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a72f3966bc5404d485e40130efefe701e">XDPPSU_TX_AUDIO_CHANNELS</a>&#160;&#160;&#160;0x0304</td></tr>
<tr class="memdesc:a72f3966bc5404d485e40130efefe701e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Used to input active channel count.  <a href="#a72f3966bc5404d485e40130efefe701e">More...</a><br/></td></tr>
<tr class="separator:a72f3966bc5404d485e40130efefe701e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4a62dd1033e79b46709a6cecff92ab78"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a4a62dd1033e79b46709a6cecff92ab78">XDPPSU_TX_AUDIO_INFO_DATA</a>&#160;&#160;&#160;0x0308</td></tr>
<tr class="memdesc:a4a62dd1033e79b46709a6cecff92ab78"><td class="mdescLeft">&#160;</td><td class="mdescRight">Word formatted as per CEA 861-C info frame.  <a href="#a4a62dd1033e79b46709a6cecff92ab78">More...</a><br/></td></tr>
<tr class="separator:a4a62dd1033e79b46709a6cecff92ab78"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4e35ebb4abdeb956bdb8d9612ea69be2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a4e35ebb4abdeb956bdb8d9612ea69be2">XDPPSU_TX_AUDIO_MAUD</a>&#160;&#160;&#160;0x0328</td></tr>
<tr class="memdesc:a4e35ebb4abdeb956bdb8d9612ea69be2"><td class="mdescLeft">&#160;</td><td class="mdescRight">M value of audio stream as computed by the DisplayPort TX core when audio and link clocks are synchronous.  <a href="#a4e35ebb4abdeb956bdb8d9612ea69be2">More...</a><br/></td></tr>
<tr class="separator:a4e35ebb4abdeb956bdb8d9612ea69be2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af176e2e67b35f97360402daad2386f9f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#af176e2e67b35f97360402daad2386f9f">XDPPSU_TX_AUDIO_NAUD</a>&#160;&#160;&#160;0x032C</td></tr>
<tr class="memdesc:af176e2e67b35f97360402daad2386f9f"><td class="mdescLeft">&#160;</td><td class="mdescRight">N value of audio stream as computed by the DisplayPort TX core when audio and link clocks are synchronous.  <a href="#af176e2e67b35f97360402daad2386f9f">More...</a><br/></td></tr>
<tr class="separator:af176e2e67b35f97360402daad2386f9f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acdaec86673f448a838cd31963d7368ff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#acdaec86673f448a838cd31963d7368ff">XDPPSU_TX_AUDIO_EXT_DATA</a>&#160;&#160;&#160;0x0330</td></tr>
<tr class="memdesc:acdaec86673f448a838cd31963d7368ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Word formatted as per extension packet.  <a href="#acdaec86673f448a838cd31963d7368ff">More...</a><br/></td></tr>
<tr class="separator:acdaec86673f448a838cd31963d7368ff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DPPSU core registers: Interrupts.</div></td></tr>
<tr class="memitem:a66cf1bc6e98aa546ba11f8a8091b1f8e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a66cf1bc6e98aa546ba11f8a8091b1f8e">XDPPSU_INTR_STATUS</a>&#160;&#160;&#160;0x03A0</td></tr>
<tr class="memdesc:a66cf1bc6e98aa546ba11f8a8091b1f8e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status for interrupt events.  <a href="#a66cf1bc6e98aa546ba11f8a8091b1f8e">More...</a><br/></td></tr>
<tr class="separator:a66cf1bc6e98aa546ba11f8a8091b1f8e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7961eb41e1c88de739f7462d44818b4c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a7961eb41e1c88de739f7462d44818b4c">XDPPSU_INTR_MASK</a>&#160;&#160;&#160;0x03A4</td></tr>
<tr class="memdesc:a7961eb41e1c88de739f7462d44818b4c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Masks the specified interrupt sources.  <a href="#a7961eb41e1c88de739f7462d44818b4c">More...</a><br/></td></tr>
<tr class="separator:a7961eb41e1c88de739f7462d44818b4c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4df905812adc82df8d8c84ade4093acf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a4df905812adc82df8d8c84ade4093acf">XDPPSU_INTR_EN</a>&#160;&#160;&#160;0x03A8</td></tr>
<tr class="memdesc:a4df905812adc82df8d8c84ade4093acf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt enable register.  <a href="#a4df905812adc82df8d8c84ade4093acf">More...</a><br/></td></tr>
<tr class="separator:a4df905812adc82df8d8c84ade4093acf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aed1c38a089b2e11a4e182a0d7d3d7581"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#aed1c38a089b2e11a4e182a0d7d3d7581">XDPPSU_INTR_DIS</a>&#160;&#160;&#160;0x03AC</td></tr>
<tr class="memdesc:aed1c38a089b2e11a4e182a0d7d3d7581"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt disable register.  <a href="#aed1c38a089b2e11a4e182a0d7d3d7581">More...</a><br/></td></tr>
<tr class="separator:aed1c38a089b2e11a4e182a0d7d3d7581"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DPPSU core masks, shifts, and register values.</div></td></tr>
<tr class="memitem:af641cdc72bb85675494a1c463904f8e1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#af641cdc72bb85675494a1c463904f8e1">XDPPSU_LINK_BW_SET_162GBPS</a>&#160;&#160;&#160;0x06</td></tr>
<tr class="memdesc:af641cdc72bb85675494a1c463904f8e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">1.62 Gbps link rate.  <a href="#af641cdc72bb85675494a1c463904f8e1">More...</a><br/></td></tr>
<tr class="separator:af641cdc72bb85675494a1c463904f8e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a826616f141ab667c2f91c83507ce2322"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a826616f141ab667c2f91c83507ce2322">XDPPSU_LINK_BW_SET_270GBPS</a>&#160;&#160;&#160;0x0A</td></tr>
<tr class="memdesc:a826616f141ab667c2f91c83507ce2322"><td class="mdescLeft">&#160;</td><td class="mdescRight">2.70 Gbps link rate.  <a href="#a826616f141ab667c2f91c83507ce2322">More...</a><br/></td></tr>
<tr class="separator:a826616f141ab667c2f91c83507ce2322"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab01ff3802386be5d138cf5a9af031783"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ab01ff3802386be5d138cf5a9af031783">XDPPSU_LINK_BW_SET_540GBPS</a>&#160;&#160;&#160;0x14</td></tr>
<tr class="memdesc:ab01ff3802386be5d138cf5a9af031783"><td class="mdescLeft">&#160;</td><td class="mdescRight">5.40 Gbps link rate.  <a href="#ab01ff3802386be5d138cf5a9af031783">More...</a><br/></td></tr>
<tr class="separator:ab01ff3802386be5d138cf5a9af031783"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab2400bfc1fa2146da8072bbd146f4389"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ab2400bfc1fa2146da8072bbd146f4389">XDPPSU_LANE_COUNT_SET_1</a>&#160;&#160;&#160;0x01</td></tr>
<tr class="memdesc:ab2400bfc1fa2146da8072bbd146f4389"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lane count of 1.  <a href="#ab2400bfc1fa2146da8072bbd146f4389">More...</a><br/></td></tr>
<tr class="separator:ab2400bfc1fa2146da8072bbd146f4389"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a07e8772a5d5bc27127f948b47122cec4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a07e8772a5d5bc27127f948b47122cec4">XDPPSU_LANE_COUNT_SET_2</a>&#160;&#160;&#160;0x02</td></tr>
<tr class="memdesc:a07e8772a5d5bc27127f948b47122cec4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lane count of 2.  <a href="#a07e8772a5d5bc27127f948b47122cec4">More...</a><br/></td></tr>
<tr class="separator:a07e8772a5d5bc27127f948b47122cec4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8f2c84354e5bb55cd069cea5322ff051"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a8f2c84354e5bb55cd069cea5322ff051">XDPPSU_TRAINING_PATTERN_SET_OFF</a>&#160;&#160;&#160;0x0</td></tr>
<tr class="memdesc:a8f2c84354e5bb55cd069cea5322ff051"><td class="mdescLeft">&#160;</td><td class="mdescRight">Training off.  <a href="#a8f2c84354e5bb55cd069cea5322ff051">More...</a><br/></td></tr>
<tr class="separator:a8f2c84354e5bb55cd069cea5322ff051"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9d807ffa394367098f9b64878158da17"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a9d807ffa394367098f9b64878158da17">XDPPSU_TRAINING_PATTERN_SET_TP1</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="memdesc:a9d807ffa394367098f9b64878158da17"><td class="mdescLeft">&#160;</td><td class="mdescRight">Training pattern 1 used for clock recovery.  <a href="#a9d807ffa394367098f9b64878158da17">More...</a><br/></td></tr>
<tr class="separator:a9d807ffa394367098f9b64878158da17"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a44d60c953f9bcf0e6354301c5d0e8915"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a44d60c953f9bcf0e6354301c5d0e8915">XDPPSU_TRAINING_PATTERN_SET_TP2</a>&#160;&#160;&#160;0x2</td></tr>
<tr class="memdesc:a44d60c953f9bcf0e6354301c5d0e8915"><td class="mdescLeft">&#160;</td><td class="mdescRight">Training pattern 2 used for channel equalization.  <a href="#a44d60c953f9bcf0e6354301c5d0e8915">More...</a><br/></td></tr>
<tr class="separator:a44d60c953f9bcf0e6354301c5d0e8915"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acf6992e1d3931bb1f6ceb82666b5d354"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#acf6992e1d3931bb1f6ceb82666b5d354">XDPPSU_TRAINING_PATTERN_SET_TP3</a>&#160;&#160;&#160;0x3</td></tr>
<tr class="memdesc:acf6992e1d3931bb1f6ceb82666b5d354"><td class="mdescLeft">&#160;</td><td class="mdescRight">Training pattern 3 used for channel equalization for cores with DP v1.2.  <a href="#acf6992e1d3931bb1f6ceb82666b5d354">More...</a><br/></td></tr>
<tr class="separator:acf6992e1d3931bb1f6ceb82666b5d354"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac594adc36322663f5281ce39a5bedf91"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ac594adc36322663f5281ce39a5bedf91">XDPPSU_LINK_QUAL_PATTERN_SET_OFF</a>&#160;&#160;&#160;0x0</td></tr>
<tr class="memdesc:ac594adc36322663f5281ce39a5bedf91"><td class="mdescLeft">&#160;</td><td class="mdescRight">Link quality test pattern not transmitted.  <a href="#ac594adc36322663f5281ce39a5bedf91">More...</a><br/></td></tr>
<tr class="separator:ac594adc36322663f5281ce39a5bedf91"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3bd3f2849a7d89187c1dd623dea3c24d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a3bd3f2849a7d89187c1dd623dea3c24d">XDPPSU_LINK_QUAL_PATTERN_SET_D102_TEST</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="memdesc:a3bd3f2849a7d89187c1dd623dea3c24d"><td class="mdescLeft">&#160;</td><td class="mdescRight">D10.2 unscrambled test pattern transmitted.  <a href="#a3bd3f2849a7d89187c1dd623dea3c24d">More...</a><br/></td></tr>
<tr class="separator:a3bd3f2849a7d89187c1dd623dea3c24d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae5b3264185b7d7eb74026d8c9cba83fc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ae5b3264185b7d7eb74026d8c9cba83fc">XDPPSU_LINK_QUAL_PATTERN_SET_SER_MES</a>&#160;&#160;&#160;0x2</td></tr>
<tr class="memdesc:ae5b3264185b7d7eb74026d8c9cba83fc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Symbol error rate measurement pattern transmitted.  <a href="#ae5b3264185b7d7eb74026d8c9cba83fc">More...</a><br/></td></tr>
<tr class="separator:ae5b3264185b7d7eb74026d8c9cba83fc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a152631a04673c1ba60de6b167f200ff0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a152631a04673c1ba60de6b167f200ff0">XDPPSU_LINK_QUAL_PATTERN_SET_PRBS7</a>&#160;&#160;&#160;0x3</td></tr>
<tr class="memdesc:a152631a04673c1ba60de6b167f200ff0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pseudo random bit sequence 7 transmitted.  <a href="#a152631a04673c1ba60de6b167f200ff0">More...</a><br/></td></tr>
<tr class="separator:a152631a04673c1ba60de6b167f200ff0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adc73b05c94da6e1c36d0bebbc8957488"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#adc73b05c94da6e1c36d0bebbc8957488">XDPPSU_LINK_QUAL_PATTERN_SET_80B_CUSTOM</a>&#160;&#160;&#160;0x4</td></tr>
<tr class="memdesc:adc73b05c94da6e1c36d0bebbc8957488"><td class="mdescLeft">&#160;</td><td class="mdescRight">80-bit custom pattern.  <a href="#adc73b05c94da6e1c36d0bebbc8957488">More...</a><br/></td></tr>
<tr class="separator:adc73b05c94da6e1c36d0bebbc8957488"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a231835618553eadbf8738d9992de34ed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a231835618553eadbf8738d9992de34ed">XDPPSU_LINK_QUAL_PATTERN_SET_HBR2_COMP</a>&#160;&#160;&#160;0x5</td></tr>
<tr class="memdesc:a231835618553eadbf8738d9992de34ed"><td class="mdescLeft">&#160;</td><td class="mdescRight">HBR2 compliance pattern.  <a href="#a231835618553eadbf8738d9992de34ed">More...</a><br/></td></tr>
<tr class="separator:a231835618553eadbf8738d9992de34ed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a932ba29315d349fc2d37fcbf92d884d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a932ba29315d349fc2d37fcbf92d884d2">XDPPSU_LINK_QUAL_PATTERN_SET_EXT_MASK</a>&#160;&#160;&#160;0x4</td></tr>
<tr class="memdesc:a932ba29315d349fc2d37fcbf92d884d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Used for HBR2 compliance and 80-bit custom patterns.  <a href="#a932ba29315d349fc2d37fcbf92d884d2">More...</a><br/></td></tr>
<tr class="separator:a932ba29315d349fc2d37fcbf92d884d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4bfaf0278473da546bc1b6d36b89fdbb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a4bfaf0278473da546bc1b6d36b89fdbb">XDPPSU_VERSION_INTER_REV_MASK</a>&#160;&#160;&#160;0x0000000F</td></tr>
<tr class="memdesc:a4bfaf0278473da546bc1b6d36b89fdbb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Internal revision.  <a href="#a4bfaf0278473da546bc1b6d36b89fdbb">More...</a><br/></td></tr>
<tr class="separator:a4bfaf0278473da546bc1b6d36b89fdbb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5d53acb81f244f49bb023b24d11837e9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a5d53acb81f244f49bb023b24d11837e9">XDPPSU_VERSION_CORE_PATCH_MASK</a>&#160;&#160;&#160;0x00000030</td></tr>
<tr class="memdesc:a5d53acb81f244f49bb023b24d11837e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core patch details.  <a href="#a5d53acb81f244f49bb023b24d11837e9">More...</a><br/></td></tr>
<tr class="separator:a5d53acb81f244f49bb023b24d11837e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6101169897ad4c4cff60a1cd8d9feb12"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a6101169897ad4c4cff60a1cd8d9feb12">XDPPSU_VERSION_CORE_PATCH_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:a6101169897ad4c4cff60a1cd8d9feb12"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for core patch details.  <a href="#a6101169897ad4c4cff60a1cd8d9feb12">More...</a><br/></td></tr>
<tr class="separator:a6101169897ad4c4cff60a1cd8d9feb12"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a774c413c2cffe51cae5c8156cf740afc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a774c413c2cffe51cae5c8156cf740afc">XDPPSU_VERSION_CORE_VER_REV_MASK</a>&#160;&#160;&#160;0x000000C0</td></tr>
<tr class="memdesc:a774c413c2cffe51cae5c8156cf740afc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core version revision.  <a href="#a774c413c2cffe51cae5c8156cf740afc">More...</a><br/></td></tr>
<tr class="separator:a774c413c2cffe51cae5c8156cf740afc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae46d9afaf4347d48ca7c12393b871dce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ae46d9afaf4347d48ca7c12393b871dce">XDPPSU_VERSION_CORE_VER_REV_SHIFT</a>&#160;&#160;&#160;12</td></tr>
<tr class="memdesc:ae46d9afaf4347d48ca7c12393b871dce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for core version revision.  <a href="#ae46d9afaf4347d48ca7c12393b871dce">More...</a><br/></td></tr>
<tr class="separator:ae46d9afaf4347d48ca7c12393b871dce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afe2062db881f2df560a2e899f09290b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#afe2062db881f2df560a2e899f09290b8">XDPPSU_VERSION_CORE_VER_MNR_MASK</a>&#160;&#160;&#160;0x00000F00</td></tr>
<tr class="memdesc:afe2062db881f2df560a2e899f09290b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core minor version.  <a href="#afe2062db881f2df560a2e899f09290b8">More...</a><br/></td></tr>
<tr class="separator:afe2062db881f2df560a2e899f09290b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0587f207575f813f9614bd249c0e4785"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a0587f207575f813f9614bd249c0e4785">XDPPSU_VERSION_CORE_VER_MNR_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a0587f207575f813f9614bd249c0e4785"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for core minor version.  <a href="#a0587f207575f813f9614bd249c0e4785">More...</a><br/></td></tr>
<tr class="separator:a0587f207575f813f9614bd249c0e4785"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6aa9d8689866ac3282305549d70fad0b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a6aa9d8689866ac3282305549d70fad0b">XDPPSU_VERSION_CORE_VER_MJR_MASK</a>&#160;&#160;&#160;0x0000F000</td></tr>
<tr class="memdesc:a6aa9d8689866ac3282305549d70fad0b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core major version.  <a href="#a6aa9d8689866ac3282305549d70fad0b">More...</a><br/></td></tr>
<tr class="separator:a6aa9d8689866ac3282305549d70fad0b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adb1f21a062fafd98d6ca9a769661c806"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#adb1f21a062fafd98d6ca9a769661c806">XDPPSU_VERSION_CORE_VER_MJR_SHIFT</a>&#160;&#160;&#160;24</td></tr>
<tr class="memdesc:adb1f21a062fafd98d6ca9a769661c806"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for core major version.  <a href="#adb1f21a062fafd98d6ca9a769661c806">More...</a><br/></td></tr>
<tr class="separator:adb1f21a062fafd98d6ca9a769661c806"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1932581ae96af65a9525e241134a3afe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a1932581ae96af65a9525e241134a3afe">XDPPSU_CORE_ID_TYPE_MASK</a>&#160;&#160;&#160;0x0000000F</td></tr>
<tr class="memdesc:a1932581ae96af65a9525e241134a3afe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core type.  <a href="#a1932581ae96af65a9525e241134a3afe">More...</a><br/></td></tr>
<tr class="separator:a1932581ae96af65a9525e241134a3afe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af51a9b5493acbb0f6275fb71ed88f052"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#af51a9b5493acbb0f6275fb71ed88f052">XDPPSU_CORE_ID_TYPE_TX</a>&#160;&#160;&#160;0x0</td></tr>
<tr class="memdesc:af51a9b5493acbb0f6275fb71ed88f052"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core is a transmitter.  <a href="#af51a9b5493acbb0f6275fb71ed88f052">More...</a><br/></td></tr>
<tr class="separator:af51a9b5493acbb0f6275fb71ed88f052"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0a7400909e42e7f017683666bb8a08a6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a0a7400909e42e7f017683666bb8a08a6">XDPPSU_CORE_ID_TYPE_RX</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="memdesc:a0a7400909e42e7f017683666bb8a08a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core is a receiver.  <a href="#a0a7400909e42e7f017683666bb8a08a6">More...</a><br/></td></tr>
<tr class="separator:a0a7400909e42e7f017683666bb8a08a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae73f897b46a59fdbaea6de897c93e924"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ae73f897b46a59fdbaea6de897c93e924">XDPPSU_CORE_ID_DP_REV_MASK</a>&#160;&#160;&#160;0x000000F0</td></tr>
<tr class="memdesc:ae73f897b46a59fdbaea6de897c93e924"><td class="mdescLeft">&#160;</td><td class="mdescRight">DisplayPort protocol revision.  <a href="#ae73f897b46a59fdbaea6de897c93e924">More...</a><br/></td></tr>
<tr class="separator:ae73f897b46a59fdbaea6de897c93e924"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4688b96899aa1f6a1b14fafe6f6fbe9a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a4688b96899aa1f6a1b14fafe6f6fbe9a">XDPPSU_CORE_ID_DP_REV_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:a4688b96899aa1f6a1b14fafe6f6fbe9a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for DisplayPort protocol revision.  <a href="#a4688b96899aa1f6a1b14fafe6f6fbe9a">More...</a><br/></td></tr>
<tr class="separator:a4688b96899aa1f6a1b14fafe6f6fbe9a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5425dfe0c16d2930f19cdf73634d1e89"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a5425dfe0c16d2930f19cdf73634d1e89">XDPPSU_CORE_ID_DP_MNR_VER_MASK</a>&#160;&#160;&#160;0x00000F00</td></tr>
<tr class="memdesc:a5425dfe0c16d2930f19cdf73634d1e89"><td class="mdescLeft">&#160;</td><td class="mdescRight">DisplayPort protocol minor version.  <a href="#a5425dfe0c16d2930f19cdf73634d1e89">More...</a><br/></td></tr>
<tr class="separator:a5425dfe0c16d2930f19cdf73634d1e89"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9aecb46049a8c94c958f6cdcb69e23f3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a9aecb46049a8c94c958f6cdcb69e23f3">XDPPSU_CORE_ID_DP_MNR_VER_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a9aecb46049a8c94c958f6cdcb69e23f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for DisplayPort protocol major version.  <a href="#a9aecb46049a8c94c958f6cdcb69e23f3">More...</a><br/></td></tr>
<tr class="separator:a9aecb46049a8c94c958f6cdcb69e23f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3f23aee2514b6d668cda67d125a0c844"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a3f23aee2514b6d668cda67d125a0c844">XDPPSU_CORE_ID_DP_MJR_VER_MASK</a>&#160;&#160;&#160;0x0000F000</td></tr>
<tr class="memdesc:a3f23aee2514b6d668cda67d125a0c844"><td class="mdescLeft">&#160;</td><td class="mdescRight">DisplayPort protocol major version.  <a href="#a3f23aee2514b6d668cda67d125a0c844">More...</a><br/></td></tr>
<tr class="separator:a3f23aee2514b6d668cda67d125a0c844"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a72f20d276edd42a8ba79582767527d9b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a72f20d276edd42a8ba79582767527d9b">XDPPSU_CORE_ID_DP_MJR_VER_SHIFT</a>&#160;&#160;&#160;24</td></tr>
<tr class="memdesc:a72f20d276edd42a8ba79582767527d9b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for DisplayPort protocol major version.  <a href="#a72f20d276edd42a8ba79582767527d9b">More...</a><br/></td></tr>
<tr class="separator:a72f20d276edd42a8ba79582767527d9b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2c3279d5ddfa43e543be27d903cc4748"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a2c3279d5ddfa43e543be27d903cc4748">XDPPSU_AUX_CMD_NBYTES_TRANSFER_MASK</a>&#160;&#160;&#160;0x0000000F</td></tr>
<tr class="memdesc:a2c3279d5ddfa43e543be27d903cc4748"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of bytes to transfer with the current AUX command.  <a href="#a2c3279d5ddfa43e543be27d903cc4748">More...</a><br/></td></tr>
<tr class="separator:a2c3279d5ddfa43e543be27d903cc4748"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a372eca59396bba202909bd3456e24030"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a372eca59396bba202909bd3456e24030">XDPPSU_AUX_CMD_MASK</a>&#160;&#160;&#160;0x00000F00</td></tr>
<tr class="memdesc:a372eca59396bba202909bd3456e24030"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX command.  <a href="#a372eca59396bba202909bd3456e24030">More...</a><br/></td></tr>
<tr class="separator:a372eca59396bba202909bd3456e24030"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6879dc40fb052b5bdb99acdd18929d6c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a6879dc40fb052b5bdb99acdd18929d6c">XDPPSU_AUX_CMD_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:a6879dc40fb052b5bdb99acdd18929d6c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for command.  <a href="#a6879dc40fb052b5bdb99acdd18929d6c">More...</a><br/></td></tr>
<tr class="separator:a6879dc40fb052b5bdb99acdd18929d6c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad871a4a4fbd142acbd47f51a04795427"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ad871a4a4fbd142acbd47f51a04795427">XDPPSU_AUX_CMD_I2C_WRITE</a>&#160;&#160;&#160;0x0</td></tr>
<tr class="memdesc:ad871a4a4fbd142acbd47f51a04795427"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2C-over-AUX write command.  <a href="#ad871a4a4fbd142acbd47f51a04795427">More...</a><br/></td></tr>
<tr class="separator:ad871a4a4fbd142acbd47f51a04795427"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5e35cfa767446df01b353e4087c129c9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a5e35cfa767446df01b353e4087c129c9">XDPPSU_AUX_CMD_I2C_READ</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="memdesc:a5e35cfa767446df01b353e4087c129c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2C-over-AUX read command.  <a href="#a5e35cfa767446df01b353e4087c129c9">More...</a><br/></td></tr>
<tr class="separator:a5e35cfa767446df01b353e4087c129c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afadde8f14c83776643cc1d40eb7a1c0c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#afadde8f14c83776643cc1d40eb7a1c0c">XDPPSU_AUX_CMD_I2C_WRITE_STATUS</a>&#160;&#160;&#160;0x2</td></tr>
<tr class="memdesc:afadde8f14c83776643cc1d40eb7a1c0c"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2C-over-AUX write status command.  <a href="#afadde8f14c83776643cc1d40eb7a1c0c">More...</a><br/></td></tr>
<tr class="separator:afadde8f14c83776643cc1d40eb7a1c0c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aca2a052c8d143f0af11b296642b25025"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#aca2a052c8d143f0af11b296642b25025">XDPPSU_AUX_CMD_I2C_WRITE_MOT</a>&#160;&#160;&#160;0x4</td></tr>
<tr class="memdesc:aca2a052c8d143f0af11b296642b25025"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2C-over-AUX write MOT (middle-of-transaction) command.  <a href="#aca2a052c8d143f0af11b296642b25025">More...</a><br/></td></tr>
<tr class="separator:aca2a052c8d143f0af11b296642b25025"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adca9517232a60a867d954c983059a7a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#adca9517232a60a867d954c983059a7a2">XDPPSU_AUX_CMD_I2C_READ_MOT</a>&#160;&#160;&#160;0x5</td></tr>
<tr class="memdesc:adca9517232a60a867d954c983059a7a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2C-over-AUX read MOT (middle-of-transaction) command.  <a href="#adca9517232a60a867d954c983059a7a2">More...</a><br/></td></tr>
<tr class="separator:adca9517232a60a867d954c983059a7a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac8ac078b0a494f750832471ff8ac124b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ac8ac078b0a494f750832471ff8ac124b">XDPPSU_AUX_CMD_I2C_WRITE_STATUS_MOT</a>&#160;&#160;&#160;0x6</td></tr>
<tr class="memdesc:ac8ac078b0a494f750832471ff8ac124b"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2C-over-AUX write status MOT (middle-of- transaction) command.  <a href="#ac8ac078b0a494f750832471ff8ac124b">More...</a><br/></td></tr>
<tr class="separator:ac8ac078b0a494f750832471ff8ac124b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa00034da8faac0abfb2c515aab654963"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#aa00034da8faac0abfb2c515aab654963">XDPPSU_AUX_CMD_WRITE</a>&#160;&#160;&#160;0x8</td></tr>
<tr class="memdesc:aa00034da8faac0abfb2c515aab654963"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX write command.  <a href="#aa00034da8faac0abfb2c515aab654963">More...</a><br/></td></tr>
<tr class="separator:aa00034da8faac0abfb2c515aab654963"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad51f02c0576e8074f3c00e4182ecaab9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ad51f02c0576e8074f3c00e4182ecaab9">XDPPSU_AUX_CMD_READ</a>&#160;&#160;&#160;0x9</td></tr>
<tr class="memdesc:ad51f02c0576e8074f3c00e4182ecaab9"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX read command.  <a href="#ad51f02c0576e8074f3c00e4182ecaab9">More...</a><br/></td></tr>
<tr class="separator:ad51f02c0576e8074f3c00e4182ecaab9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8fffddf81157839ad110cd05e4003918"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a8fffddf81157839ad110cd05e4003918">XDPPSU_AUX_CMD_ADDR_ONLY_TRANSFER_EN</a>&#160;&#160;&#160;0x00001000</td></tr>
<tr class="memdesc:a8fffddf81157839ad110cd05e4003918"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address only transfer enable (STOP will be sent after command).  <a href="#a8fffddf81157839ad110cd05e4003918">More...</a><br/></td></tr>
<tr class="separator:a8fffddf81157839ad110cd05e4003918"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2993f0909955fb9addd467a4796185ca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a2993f0909955fb9addd467a4796185ca">XDPPSU_AUX_CLK_DIVIDER_VAL_MASK</a>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="memdesc:a2993f0909955fb9addd467a4796185ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock divider value.  <a href="#a2993f0909955fb9addd467a4796185ca">More...</a><br/></td></tr>
<tr class="separator:a2993f0909955fb9addd467a4796185ca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8a8f30af26ba6f80237373d534a05e4d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a8a8f30af26ba6f80237373d534a05e4d">XDPPSU_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK</a>&#160;&#160;&#160;0x0000FF00</td></tr>
<tr class="memdesc:a8a8f30af26ba6f80237373d534a05e4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX (noise) signal width filter.  <a href="#a8a8f30af26ba6f80237373d534a05e4d">More...</a><br/></td></tr>
<tr class="separator:a8a8f30af26ba6f80237373d534a05e4d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a53109f41484d23df39e174644222ba46"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a53109f41484d23df39e174644222ba46">XDPPSU_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:a53109f41484d23df39e174644222ba46"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for AUX signal width filter.  <a href="#a53109f41484d23df39e174644222ba46">More...</a><br/></td></tr>
<tr class="separator:a53109f41484d23df39e174644222ba46"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abe45f09e082e6ceecb66597575dac0e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#abe45f09e082e6ceecb66597575dac0e7">XDPPSU_INTERRUPT_SIG_STATE_HPD_STATE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:abe45f09e082e6ceecb66597575dac0e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Raw state of the HPD pin on the DP connector.  <a href="#abe45f09e082e6ceecb66597575dac0e7">More...</a><br/></td></tr>
<tr class="separator:abe45f09e082e6ceecb66597575dac0e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4d3e7112cc860981d1becb976cc6e2a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a4d3e7112cc860981d1becb976cc6e2a1">XDPPSU_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:a4d3e7112cc860981d1becb976cc6e2a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">A request is currently being sent.  <a href="#a4d3e7112cc860981d1becb976cc6e2a1">More...</a><br/></td></tr>
<tr class="separator:a4d3e7112cc860981d1becb976cc6e2a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af6414260592c508ef5410355a8940834"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#af6414260592c508ef5410355a8940834">XDPPSU_INTERRUPT_SIG_STATE_REPLY_STATE_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:af6414260592c508ef5410355a8940834"><td class="mdescLeft">&#160;</td><td class="mdescRight">A reply is currently being received.  <a href="#af6414260592c508ef5410355a8940834">More...</a><br/></td></tr>
<tr class="separator:af6414260592c508ef5410355a8940834"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a08ade06a64e915ca736c49fb5e6836ef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a08ade06a64e915ca736c49fb5e6836ef">XDPPSU_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:a08ade06a64e915ca736c49fb5e6836ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">A reply timeout has occurred.  <a href="#a08ade06a64e915ca736c49fb5e6836ef">More...</a><br/></td></tr>
<tr class="separator:a08ade06a64e915ca736c49fb5e6836ef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abbbaa950f9da6867d9d5522cb4923c05"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#abbbaa950f9da6867d9d5522cb4923c05">XDPPSU_AUX_REPLY_CODE_ACK</a>&#160;&#160;&#160;0x0</td></tr>
<tr class="memdesc:abbbaa950f9da6867d9d5522cb4923c05"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX command ACKed.  <a href="#abbbaa950f9da6867d9d5522cb4923c05">More...</a><br/></td></tr>
<tr class="separator:abbbaa950f9da6867d9d5522cb4923c05"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3f1448602c1a706793619c680a84d79e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a3f1448602c1a706793619c680a84d79e">XDPPSU_AUX_REPLY_CODE_I2C_ACK</a>&#160;&#160;&#160;0x0</td></tr>
<tr class="memdesc:a3f1448602c1a706793619c680a84d79e"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2C-over-AUX command not ACKed.  <a href="#a3f1448602c1a706793619c680a84d79e">More...</a><br/></td></tr>
<tr class="separator:a3f1448602c1a706793619c680a84d79e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5d1d3c855786c36190951ea9d8d97e63"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a5d1d3c855786c36190951ea9d8d97e63">XDPPSU_AUX_REPLY_CODE_NACK</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="memdesc:a5d1d3c855786c36190951ea9d8d97e63"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX command not ACKed.  <a href="#a5d1d3c855786c36190951ea9d8d97e63">More...</a><br/></td></tr>
<tr class="separator:a5d1d3c855786c36190951ea9d8d97e63"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a256a6402fa69b0a4ba549bb5e1dd92a5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a256a6402fa69b0a4ba549bb5e1dd92a5">XDPPSU_AUX_REPLY_CODE_DEFER</a>&#160;&#160;&#160;0x2</td></tr>
<tr class="memdesc:a256a6402fa69b0a4ba549bb5e1dd92a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX command deferred.  <a href="#a256a6402fa69b0a4ba549bb5e1dd92a5">More...</a><br/></td></tr>
<tr class="separator:a256a6402fa69b0a4ba549bb5e1dd92a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a94f369541d6351ac8520252f0234fa11"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a94f369541d6351ac8520252f0234fa11">XDPPSU_AUX_REPLY_CODE_I2C_NACK</a>&#160;&#160;&#160;0x4</td></tr>
<tr class="memdesc:a94f369541d6351ac8520252f0234fa11"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2C-over-AUX command not ACKed.  <a href="#a94f369541d6351ac8520252f0234fa11">More...</a><br/></td></tr>
<tr class="separator:a94f369541d6351ac8520252f0234fa11"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a61a30cbd5c74f7c4e446cea776010d37"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a61a30cbd5c74f7c4e446cea776010d37">XDPPSU_AUX_REPLY_CODE_I2C_DEFER</a>&#160;&#160;&#160;0x8</td></tr>
<tr class="memdesc:a61a30cbd5c74f7c4e446cea776010d37"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2C-over-AUX command deferred.  <a href="#a61a30cbd5c74f7c4e446cea776010d37">More...</a><br/></td></tr>
<tr class="separator:a61a30cbd5c74f7c4e446cea776010d37"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a147de67b6171acd49f0c14722980cf88"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a147de67b6171acd49f0c14722980cf88">XDPPSU_REPLY_STATUS_REPLY_RECEIVED_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:a147de67b6171acd49f0c14722980cf88"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX transaction is complete and a valid reply transaction received.  <a href="#a147de67b6171acd49f0c14722980cf88">More...</a><br/></td></tr>
<tr class="separator:a147de67b6171acd49f0c14722980cf88"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0fcf6a885af08954316e8fa77914a437"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a0fcf6a885af08954316e8fa77914a437">XDPPSU_REPLY_STATUS_REPLY_IN_PROGRESS_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:a0fcf6a885af08954316e8fa77914a437"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX reply is currently being received.  <a href="#a0fcf6a885af08954316e8fa77914a437">More...</a><br/></td></tr>
<tr class="separator:a0fcf6a885af08954316e8fa77914a437"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a28186a7d8691e88a0b470365a4e6ccd7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a28186a7d8691e88a0b470365a4e6ccd7">XDPPSU_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:a28186a7d8691e88a0b470365a4e6ccd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX request is currently being transmitted.  <a href="#a28186a7d8691e88a0b470365a4e6ccd7">More...</a><br/></td></tr>
<tr class="separator:a28186a7d8691e88a0b470365a4e6ccd7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5451b49271e361e747472252d4bf19cd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a5451b49271e361e747472252d4bf19cd">XDPPSU_REPLY_STATUS_REPLY_ERROR_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:a5451b49271e361e747472252d4bf19cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Detected an error in the AUX reply of the most recent transaction.  <a href="#a5451b49271e361e747472252d4bf19cd">More...</a><br/></td></tr>
<tr class="separator:a5451b49271e361e747472252d4bf19cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a881e39fa5e38787ed558c988de819f24"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a881e39fa5e38787ed558c988de819f24">XDPPSU_REPLY_STATUS_REPLY_STATUS_STATE_MASK</a>&#160;&#160;&#160;0x00000FF0</td></tr>
<tr class="memdesc:a881e39fa5e38787ed558c988de819f24"><td class="mdescLeft">&#160;</td><td class="mdescRight">Internal AUX reply state machine status bits.  <a href="#a881e39fa5e38787ed558c988de819f24">More...</a><br/></td></tr>
<tr class="separator:a881e39fa5e38787ed558c988de819f24"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3989bff7e9babcb97ac85f2760bea47c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a3989bff7e9babcb97ac85f2760bea47c">XDPPSU_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:a3989bff7e9babcb97ac85f2760bea47c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for the internal AUX reply state machine status.  <a href="#a3989bff7e9babcb97ac85f2760bea47c">More...</a><br/></td></tr>
<tr class="separator:a3989bff7e9babcb97ac85f2760bea47c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adf93e2b972e6ad2a0217efff40d0c605"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#adf93e2b972e6ad2a0217efff40d0c605">XDPPSU_MAIN_STREAM_POLARITY_HSYNC_POL_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:adf93e2b972e6ad2a0217efff40d0c605"><td class="mdescLeft">&#160;</td><td class="mdescRight">Polarity of the horizontal sync pulse.  <a href="#adf93e2b972e6ad2a0217efff40d0c605">More...</a><br/></td></tr>
<tr class="separator:adf93e2b972e6ad2a0217efff40d0c605"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6165afdbbd6e43863b5dec77fbff7255"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a6165afdbbd6e43863b5dec77fbff7255">XDPPSU_MAIN_STREAM_POLARITY_VSYNC_POL_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:a6165afdbbd6e43863b5dec77fbff7255"><td class="mdescLeft">&#160;</td><td class="mdescRight">Polarity of the vertical sync pulse.  <a href="#a6165afdbbd6e43863b5dec77fbff7255">More...</a><br/></td></tr>
<tr class="separator:a6165afdbbd6e43863b5dec77fbff7255"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae227c02effff3397f8a882aaf587b436"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ae227c02effff3397f8a882aaf587b436">XDPPSU_MAIN_STREAM_POLARITY_VSYNC_POL_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ae227c02effff3397f8a882aaf587b436"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for polarity of the vertical sync pulse.  <a href="#ae227c02effff3397f8a882aaf587b436">More...</a><br/></td></tr>
<tr class="separator:ae227c02effff3397f8a882aaf587b436"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a91cf45127ce9176bb5daf96f07c8cddc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a91cf45127ce9176bb5daf96f07c8cddc">XDPPSU_MAIN_STREAM_MISC0_SYNC_CLK_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:a91cf45127ce9176bb5daf96f07c8cddc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Synchronous clock.  <a href="#a91cf45127ce9176bb5daf96f07c8cddc">More...</a><br/></td></tr>
<tr class="separator:a91cf45127ce9176bb5daf96f07c8cddc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a75ce663ac0c55c70e31f29771291bd5e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a75ce663ac0c55c70e31f29771291bd5e">XDPPSU_MAIN_STREAM_MISC0_COMPONENT_FORMAT_MASK</a>&#160;&#160;&#160;0x00000006</td></tr>
<tr class="memdesc:a75ce663ac0c55c70e31f29771291bd5e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Component format.  <a href="#a75ce663ac0c55c70e31f29771291bd5e">More...</a><br/></td></tr>
<tr class="separator:a75ce663ac0c55c70e31f29771291bd5e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2db3e057d0bf4c18c078c8c6c1c6e214"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a2db3e057d0bf4c18c078c8c6c1c6e214">XDPPSU_MAIN_STREAM_MISC0_COMPONENT_FORMAT_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:a2db3e057d0bf4c18c078c8c6c1c6e214"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for component format.  <a href="#a2db3e057d0bf4c18c078c8c6c1c6e214">More...</a><br/></td></tr>
<tr class="separator:a2db3e057d0bf4c18c078c8c6c1c6e214"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a62cef3c8f37c23bbcb361cf27e78b79a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a62cef3c8f37c23bbcb361cf27e78b79a">XDPPSU_MAIN_STREAM_MISC0_COMPONENT_FORMAT_RGB</a>&#160;&#160;&#160;0x0</td></tr>
<tr class="memdesc:a62cef3c8f37c23bbcb361cf27e78b79a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stream's component format is RGB.  <a href="#a62cef3c8f37c23bbcb361cf27e78b79a">More...</a><br/></td></tr>
<tr class="separator:a62cef3c8f37c23bbcb361cf27e78b79a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa7f01b729a14459dd1dd702396841e67"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#aa7f01b729a14459dd1dd702396841e67">XDPPSU_MAIN_STREAM_MISC0_COMPONENT_FORMAT_YCBCR422</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="memdesc:aa7f01b729a14459dd1dd702396841e67"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stream's component format is YcbCr 4:2:2.  <a href="#aa7f01b729a14459dd1dd702396841e67">More...</a><br/></td></tr>
<tr class="separator:aa7f01b729a14459dd1dd702396841e67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acf4d40b05aab671f8d7339ce3b3a1bff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#acf4d40b05aab671f8d7339ce3b3a1bff">XDPPSU_MAIN_STREAM_MISC0_COMPONENT_FORMAT_YCBCR444</a>&#160;&#160;&#160;0x2</td></tr>
<tr class="memdesc:acf4d40b05aab671f8d7339ce3b3a1bff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stream's component format is YcbCr 4:4:4.  <a href="#acf4d40b05aab671f8d7339ce3b3a1bff">More...</a><br/></td></tr>
<tr class="separator:acf4d40b05aab671f8d7339ce3b3a1bff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aac1319fb0218b78cd03a735255f973f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#aac1319fb0218b78cd03a735255f973f5">XDPPSU_MAIN_STREAM_MISC0_DYNAMIC_RANGE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:aac1319fb0218b78cd03a735255f973f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Dynamic range.  <a href="#aac1319fb0218b78cd03a735255f973f5">More...</a><br/></td></tr>
<tr class="separator:aac1319fb0218b78cd03a735255f973f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a848bedf3fe17154e8b43d5dc9001021d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a848bedf3fe17154e8b43d5dc9001021d">XDPPSU_MAIN_STREAM_MISC0_DYNAMIC_RANGE_SHIFT</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:a848bedf3fe17154e8b43d5dc9001021d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for dynamic range.  <a href="#a848bedf3fe17154e8b43d5dc9001021d">More...</a><br/></td></tr>
<tr class="separator:a848bedf3fe17154e8b43d5dc9001021d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7584fd929b074b9678cc208f150084c7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a7584fd929b074b9678cc208f150084c7">XDPPSU_MAIN_STREAM_MISC0_DYNAMIC_RANGE_CEA</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:a7584fd929b074b9678cc208f150084c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">CEA range.  <a href="#a7584fd929b074b9678cc208f150084c7">More...</a><br/></td></tr>
<tr class="separator:a7584fd929b074b9678cc208f150084c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9b99ddae9071dc99417a6e82d5e124c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a9b99ddae9071dc99417a6e82d5e124c3">XDPPSU_MAIN_STREAM_MISC0_DYNAMIC_RANGE_VESA</a>&#160;&#160;&#160;0x00000000</td></tr>
<tr class="memdesc:a9b99ddae9071dc99417a6e82d5e124c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">VESA range.  <a href="#a9b99ddae9071dc99417a6e82d5e124c3">More...</a><br/></td></tr>
<tr class="separator:a9b99ddae9071dc99417a6e82d5e124c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a191ea628e4913d1a8d44043a64935f1b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a191ea628e4913d1a8d44043a64935f1b">XDPPSU_MAIN_STREAM_MISC0_YCBCR_COLORIMETRY_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:a191ea628e4913d1a8d44043a64935f1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">YCbCr colorimetry.  <a href="#a191ea628e4913d1a8d44043a64935f1b">More...</a><br/></td></tr>
<tr class="separator:a191ea628e4913d1a8d44043a64935f1b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a758fdab5131d4991458d3a515d4304ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a758fdab5131d4991458d3a515d4304ac">XDPPSU_MAIN_STREAM_MISC0_YCBCR_COLORIMETRY_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:a758fdab5131d4991458d3a515d4304ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for YCbCr colorimetry.  <a href="#a758fdab5131d4991458d3a515d4304ac">More...</a><br/></td></tr>
<tr class="separator:a758fdab5131d4991458d3a515d4304ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac1311bc1fa0ca578e1c5ef5b03830aec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ac1311bc1fa0ca578e1c5ef5b03830aec">XDPPSU_MAIN_STREAM_MISC0_YCBCR_COLORIMETRY_ITU_BT709</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ac1311bc1fa0ca578e1c5ef5b03830aec"><td class="mdescLeft">&#160;</td><td class="mdescRight">ITU709 YCbCr coefficients.  <a href="#ac1311bc1fa0ca578e1c5ef5b03830aec">More...</a><br/></td></tr>
<tr class="separator:ac1311bc1fa0ca578e1c5ef5b03830aec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aeea7a0870811c648c1f14c54b7eea604"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#aeea7a0870811c648c1f14c54b7eea604">XDPPSU_MAIN_STREAM_MISC0_YCBCR_COLORIMETRY_ITU_BT601</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:aeea7a0870811c648c1f14c54b7eea604"><td class="mdescLeft">&#160;</td><td class="mdescRight">ITU601 YCbCr coefficients.  <a href="#aeea7a0870811c648c1f14c54b7eea604">More...</a><br/></td></tr>
<tr class="separator:aeea7a0870811c648c1f14c54b7eea604"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9d547e518f891c4b31590ba71cb6ed75"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a9d547e518f891c4b31590ba71cb6ed75">XDPPSU_MAIN_STREAM_MISC0_BDC_MASK</a>&#160;&#160;&#160;0x000000E0</td></tr>
<tr class="memdesc:a9d547e518f891c4b31590ba71cb6ed75"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit depth per color component (BDC).  <a href="#a9d547e518f891c4b31590ba71cb6ed75">More...</a><br/></td></tr>
<tr class="separator:a9d547e518f891c4b31590ba71cb6ed75"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acee2c3a2e5360398cf20d669767f0838"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#acee2c3a2e5360398cf20d669767f0838">XDPPSU_MAIN_STREAM_MISC0_BDC_SHIFT</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:acee2c3a2e5360398cf20d669767f0838"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for BDC.  <a href="#acee2c3a2e5360398cf20d669767f0838">More...</a><br/></td></tr>
<tr class="separator:acee2c3a2e5360398cf20d669767f0838"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a28c8927d5dbc09c1767415b65b68ee57"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a28c8927d5dbc09c1767415b65b68ee57">XDPPSU_MAIN_STREAM_MISC0_BDC_6BPC</a>&#160;&#160;&#160;0x0</td></tr>
<tr class="memdesc:a28c8927d5dbc09c1767415b65b68ee57"><td class="mdescLeft">&#160;</td><td class="mdescRight">6 bits per component.  <a href="#a28c8927d5dbc09c1767415b65b68ee57">More...</a><br/></td></tr>
<tr class="separator:a28c8927d5dbc09c1767415b65b68ee57"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4c4cf8ebf3908d41f086aa164047dc88"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a4c4cf8ebf3908d41f086aa164047dc88">XDPPSU_MAIN_STREAM_MISC0_BDC_8BPC</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="memdesc:a4c4cf8ebf3908d41f086aa164047dc88"><td class="mdescLeft">&#160;</td><td class="mdescRight">8 bits per component.  <a href="#a4c4cf8ebf3908d41f086aa164047dc88">More...</a><br/></td></tr>
<tr class="separator:a4c4cf8ebf3908d41f086aa164047dc88"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a543471a6b6f68ec7fa64c4bdc159aef6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a543471a6b6f68ec7fa64c4bdc159aef6">XDPPSU_MAIN_STREAM_MISC0_BDC_10BPC</a>&#160;&#160;&#160;0x2</td></tr>
<tr class="memdesc:a543471a6b6f68ec7fa64c4bdc159aef6"><td class="mdescLeft">&#160;</td><td class="mdescRight">10 bits per component.  <a href="#a543471a6b6f68ec7fa64c4bdc159aef6">More...</a><br/></td></tr>
<tr class="separator:a543471a6b6f68ec7fa64c4bdc159aef6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0f4025e10b15002c31e67ff319167574"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a0f4025e10b15002c31e67ff319167574">XDPPSU_MAIN_STREAM_MISC0_BDC_12BPC</a>&#160;&#160;&#160;0x3</td></tr>
<tr class="memdesc:a0f4025e10b15002c31e67ff319167574"><td class="mdescLeft">&#160;</td><td class="mdescRight">12 bits per component.  <a href="#a0f4025e10b15002c31e67ff319167574">More...</a><br/></td></tr>
<tr class="separator:a0f4025e10b15002c31e67ff319167574"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adc5bca138020f36f2ff54990a53f3bc4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#adc5bca138020f36f2ff54990a53f3bc4">XDPPSU_MAIN_STREAM_MISC0_BDC_16BPC</a>&#160;&#160;&#160;0x4</td></tr>
<tr class="memdesc:adc5bca138020f36f2ff54990a53f3bc4"><td class="mdescLeft">&#160;</td><td class="mdescRight">16 bits per component.  <a href="#adc5bca138020f36f2ff54990a53f3bc4">More...</a><br/></td></tr>
<tr class="separator:adc5bca138020f36f2ff54990a53f3bc4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab55517d8d6c777fd0d50c2b6ec04c559"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ab55517d8d6c777fd0d50c2b6ec04c559">XDPPSU_MAIN_STREAM_MISC1_STEREO_VID_ATTR_MASK</a>&#160;&#160;&#160;0x00000006</td></tr>
<tr class="memdesc:ab55517d8d6c777fd0d50c2b6ec04c559"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stereo video attribute.  <a href="#ab55517d8d6c777fd0d50c2b6ec04c559">More...</a><br/></td></tr>
<tr class="separator:ab55517d8d6c777fd0d50c2b6ec04c559"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a64e74ed760224ac4dcfad41ac58dd34f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a64e74ed760224ac4dcfad41ac58dd34f">XDPPSU_MAIN_STREAM_MISC1_STEREO_VID_ATTR_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:a64e74ed760224ac4dcfad41ac58dd34f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for stereo video attribute.  <a href="#a64e74ed760224ac4dcfad41ac58dd34f">More...</a><br/></td></tr>
<tr class="separator:a64e74ed760224ac4dcfad41ac58dd34f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3a788946c8a8f00681b5a2493af74667"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a3a788946c8a8f00681b5a2493af74667">XDPPSU_MAIN_STREAM_MISC1_Y_ONLY_EN_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:a3a788946c8a8f00681b5a2493af74667"><td class="mdescLeft">&#160;</td><td class="mdescRight">Y only enable.  <a href="#a3a788946c8a8f00681b5a2493af74667">More...</a><br/></td></tr>
<tr class="separator:a3a788946c8a8f00681b5a2493af74667"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a14b7b68d4e2f30ef852e03eeb0743929"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a14b7b68d4e2f30ef852e03eeb0743929">XDPPSU_PHY_CONFIG_PHY_RESET_ENABLE_MASK</a>&#160;&#160;&#160;0x0000000</td></tr>
<tr class="memdesc:a14b7b68d4e2f30ef852e03eeb0743929"><td class="mdescLeft">&#160;</td><td class="mdescRight">Release reset.  <a href="#a14b7b68d4e2f30ef852e03eeb0743929">More...</a><br/></td></tr>
<tr class="separator:a14b7b68d4e2f30ef852e03eeb0743929"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a848fe33e971d0e24ed48e966024dfb9a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a848fe33e971d0e24ed48e966024dfb9a">XDPPSU_PHY_CONFIG_PHY_RESET_MASK</a>&#160;&#160;&#160;0x0000001</td></tr>
<tr class="memdesc:a848fe33e971d0e24ed48e966024dfb9a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Hold the PHY in reset.  <a href="#a848fe33e971d0e24ed48e966024dfb9a">More...</a><br/></td></tr>
<tr class="separator:a848fe33e971d0e24ed48e966024dfb9a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a65c40b0e93ec7b7f50cfec29c6f1a1e1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a65c40b0e93ec7b7f50cfec29c6f1a1e1">XDPPSU_PHY_CONFIG_GTTX_RESET_MASK</a>&#160;&#160;&#160;0x0000002</td></tr>
<tr class="memdesc:a65c40b0e93ec7b7f50cfec29c6f1a1e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Hold GTTXRESET in reset.  <a href="#a65c40b0e93ec7b7f50cfec29c6f1a1e1">More...</a><br/></td></tr>
<tr class="separator:a65c40b0e93ec7b7f50cfec29c6f1a1e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aba0f41405e22038988f7198add44b5cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#aba0f41405e22038988f7198add44b5cc">XDPPSU_PHY_CONFIG_TX_PHY_8B10BEN_MASK</a>&#160;&#160;&#160;0x0010000</td></tr>
<tr class="memdesc:aba0f41405e22038988f7198add44b5cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">8B10B encoding enable.  <a href="#aba0f41405e22038988f7198add44b5cc">More...</a><br/></td></tr>
<tr class="separator:aba0f41405e22038988f7198add44b5cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a28a9751ea84fe5ab784defeb1f5b203b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a28a9751ea84fe5ab784defeb1f5b203b">XDPPSU_PHY_CONFIG_GT_ALL_RESET_MASK</a>&#160;&#160;&#160;0x0000003</td></tr>
<tr class="memdesc:a28a9751ea84fe5ab784defeb1f5b203b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset GT and PHY.  <a href="#a28a9751ea84fe5ab784defeb1f5b203b">More...</a><br/></td></tr>
<tr class="separator:a28a9751ea84fe5ab784defeb1f5b203b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a89ac9477adf2f20000d1b6f9d4adb617"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a89ac9477adf2f20000d1b6f9d4adb617">XDPPSU_PHY_CLOCK_SELECT_162GBPS</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="memdesc:a89ac9477adf2f20000d1b6f9d4adb617"><td class="mdescLeft">&#160;</td><td class="mdescRight">1.62 Gbps link.  <a href="#a89ac9477adf2f20000d1b6f9d4adb617">More...</a><br/></td></tr>
<tr class="separator:a89ac9477adf2f20000d1b6f9d4adb617"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad41a2cbf2a3730426b20ab8b1cd7f257"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ad41a2cbf2a3730426b20ab8b1cd7f257">XDPPSU_PHY_CLOCK_SELECT_270GBPS</a>&#160;&#160;&#160;0x3</td></tr>
<tr class="memdesc:ad41a2cbf2a3730426b20ab8b1cd7f257"><td class="mdescLeft">&#160;</td><td class="mdescRight">2.70 Gbps link.  <a href="#ad41a2cbf2a3730426b20ab8b1cd7f257">More...</a><br/></td></tr>
<tr class="separator:ad41a2cbf2a3730426b20ab8b1cd7f257"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac235ac35ed4fb7136ed096c754ad0c2f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ac235ac35ed4fb7136ed096c754ad0c2f">XDPPSU_PHY_CLOCK_SELECT_540GBPS</a>&#160;&#160;&#160;0x5</td></tr>
<tr class="memdesc:ac235ac35ed4fb7136ed096c754ad0c2f"><td class="mdescLeft">&#160;</td><td class="mdescRight">5.40 Gbps link.  <a href="#ac235ac35ed4fb7136ed096c754ad0c2f">More...</a><br/></td></tr>
<tr class="separator:ac235ac35ed4fb7136ed096c754ad0c2f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab6045b54dafcce51adbb0c5899307599"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ab6045b54dafcce51adbb0c5899307599">XDPPSU_VS_LEVEL_0</a>&#160;&#160;&#160;0x3</td></tr>
<tr class="memdesc:ab6045b54dafcce51adbb0c5899307599"><td class="mdescLeft">&#160;</td><td class="mdescRight">Voltage swing level 0.  <a href="#ab6045b54dafcce51adbb0c5899307599">More...</a><br/></td></tr>
<tr class="separator:ab6045b54dafcce51adbb0c5899307599"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2b47f206d94602c469782d1ba28edec2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a2b47f206d94602c469782d1ba28edec2">XDPPSU_VS_LEVEL_1</a>&#160;&#160;&#160;0x7</td></tr>
<tr class="memdesc:a2b47f206d94602c469782d1ba28edec2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Voltage swing level 1.  <a href="#a2b47f206d94602c469782d1ba28edec2">More...</a><br/></td></tr>
<tr class="separator:a2b47f206d94602c469782d1ba28edec2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4c72080fc94aeb532a2c9f6d0e50976e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a4c72080fc94aeb532a2c9f6d0e50976e">XDPPSU_VS_LEVEL_2</a>&#160;&#160;&#160;0XB</td></tr>
<tr class="memdesc:a4c72080fc94aeb532a2c9f6d0e50976e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Voltage swing level 2.  <a href="#a4c72080fc94aeb532a2c9f6d0e50976e">More...</a><br/></td></tr>
<tr class="separator:a4c72080fc94aeb532a2c9f6d0e50976e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a379d6347dbcc32330051ceef7ec181d4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a379d6347dbcc32330051ceef7ec181d4">XDPPSU_VS_LEVEL_3</a>&#160;&#160;&#160;0xF</td></tr>
<tr class="memdesc:a379d6347dbcc32330051ceef7ec181d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Voltage swing level 3.  <a href="#a379d6347dbcc32330051ceef7ec181d4">More...</a><br/></td></tr>
<tr class="separator:a379d6347dbcc32330051ceef7ec181d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abc18a2dfe265aa067dd801da122a2f24"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#abc18a2dfe265aa067dd801da122a2f24">XDPPSU_VS_LEVEL_OFFSET</a>&#160;&#160;&#160;0x4</td></tr>
<tr class="memdesc:abc18a2dfe265aa067dd801da122a2f24"><td class="mdescLeft">&#160;</td><td class="mdescRight">Voltage swing compensation.  <a href="#abc18a2dfe265aa067dd801da122a2f24">More...</a><br/></td></tr>
<tr class="separator:abc18a2dfe265aa067dd801da122a2f24"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0f0c53eed3bb612db95cead36ee12954"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a0f0c53eed3bb612db95cead36ee12954">XDPPSU_PHY_STATUS_RESET_LANE_0_DONE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:a0f0c53eed3bb612db95cead36ee12954"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset done for lane 0.  <a href="#a0f0c53eed3bb612db95cead36ee12954">More...</a><br/></td></tr>
<tr class="separator:a0f0c53eed3bb612db95cead36ee12954"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acbc96ec2c0ce6b3659a90dedc4324b03"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#acbc96ec2c0ce6b3659a90dedc4324b03">XDPPSU_PHY_STATUS_RESET_LANE_1_DONE_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:acbc96ec2c0ce6b3659a90dedc4324b03"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset done for lane 1.  <a href="#acbc96ec2c0ce6b3659a90dedc4324b03">More...</a><br/></td></tr>
<tr class="separator:acbc96ec2c0ce6b3659a90dedc4324b03"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0481f9e3c07f6d6586cb9b053a97a4b7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a0481f9e3c07f6d6586cb9b053a97a4b7">XDPPSU_PHY_STATUS_RATE_CHANGE_LANE_0_DONE_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:a0481f9e3c07f6d6586cb9b053a97a4b7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Received PHYSTATUS pulse from GT after rate change request from lane 0.  <a href="#a0481f9e3c07f6d6586cb9b053a97a4b7">More...</a><br/></td></tr>
<tr class="separator:a0481f9e3c07f6d6586cb9b053a97a4b7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a87d2936b12e86306850adc2c5ddb44bc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a87d2936b12e86306850adc2c5ddb44bc">XDPPSU_PHY_STATUS_RATE_CHANGE_LANE_1_DONE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:a87d2936b12e86306850adc2c5ddb44bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Received PHYSTATUS pulse from GT after rate change request from lane 1.  <a href="#a87d2936b12e86306850adc2c5ddb44bc">More...</a><br/></td></tr>
<tr class="separator:a87d2936b12e86306850adc2c5ddb44bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9085fff8bbafbfe31b3305dc8978e0c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a9085fff8bbafbfe31b3305dc8978e0c3">XDPPSU_PHY_STATUS_GT_PLL_LOCK_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:a9085fff8bbafbfe31b3305dc8978e0c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">GT PLL locked status.  <a href="#a9085fff8bbafbfe31b3305dc8978e0c3">More...</a><br/></td></tr>
<tr class="separator:a9085fff8bbafbfe31b3305dc8978e0c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7d43076a9bf9d542f5ce46655c3f5ebe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a7d43076a9bf9d542f5ce46655c3f5ebe">XDPPSU_PHY_STATUS_ALL_LANES_READY_MASK</a>&#160;&#160;&#160;0x00000013</td></tr>
<tr class="memdesc:a7d43076a9bf9d542f5ce46655c3f5ebe"><td class="mdescLeft">&#160;</td><td class="mdescRight">All lanes are ready.  <a href="#a7d43076a9bf9d542f5ce46655c3f5ebe">More...</a><br/></td></tr>
<tr class="separator:a7d43076a9bf9d542f5ce46655c3f5ebe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad848b6db96fff173582cb637b421b1fa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ad848b6db96fff173582cb637b421b1fa">XDPPSU_INTR_HPD_IRQ_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ad848b6db96fff173582cb637b421b1fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Detected an IRQ framed with the proper timing on the HPD signal.  <a href="#ad848b6db96fff173582cb637b421b1fa">More...</a><br/></td></tr>
<tr class="separator:ad848b6db96fff173582cb637b421b1fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3c97c07d18d9c5a39382fb8f8f7518b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a3c97c07d18d9c5a39382fb8f8f7518b6">XDPPSU_INTR_HPD_EVENT_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:a3c97c07d18d9c5a39382fb8f8f7518b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Detected the presence of the HPD signal.  <a href="#a3c97c07d18d9c5a39382fb8f8f7518b6">More...</a><br/></td></tr>
<tr class="separator:a3c97c07d18d9c5a39382fb8f8f7518b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a541b41f7d1c9b568d4329ba9407851d0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a541b41f7d1c9b568d4329ba9407851d0">XDPPSU_INTR_REPLY_RECEIVED_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:a541b41f7d1c9b568d4329ba9407851d0"><td class="mdescLeft">&#160;</td><td class="mdescRight">An AUX reply transaction has been detected.  <a href="#a541b41f7d1c9b568d4329ba9407851d0">More...</a><br/></td></tr>
<tr class="separator:a541b41f7d1c9b568d4329ba9407851d0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a294c84ec5b18a80d4179d9e1b297bba5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a294c84ec5b18a80d4179d9e1b297bba5">XDPPSU_INTR_REPLY_TIMEOUT_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:a294c84ec5b18a80d4179d9e1b297bba5"><td class="mdescLeft">&#160;</td><td class="mdescRight">A reply timeout has occurred.  <a href="#a294c84ec5b18a80d4179d9e1b297bba5">More...</a><br/></td></tr>
<tr class="separator:a294c84ec5b18a80d4179d9e1b297bba5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a63c73ef7b94ee2b16928d5423226e636"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a63c73ef7b94ee2b16928d5423226e636">XDPPSU_INTR_HPD_PULSE_DETECTED_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:a63c73ef7b94ee2b16928d5423226e636"><td class="mdescLeft">&#160;</td><td class="mdescRight">A pulse on the HPD line was detected.  <a href="#a63c73ef7b94ee2b16928d5423226e636">More...</a><br/></td></tr>
<tr class="separator:a63c73ef7b94ee2b16928d5423226e636"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aca97dd11e3816f52fea1b6d1ef6ab182"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#aca97dd11e3816f52fea1b6d1ef6ab182">XDPPSU_INTR_EXT_PKT_TXD_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:aca97dd11e3816f52fea1b6d1ef6ab182"><td class="mdescLeft">&#160;</td><td class="mdescRight">Extended packet has been transmitted and the core is ready to accept a new packet.  <a href="#aca97dd11e3816f52fea1b6d1ef6ab182">More...</a><br/></td></tr>
<tr class="separator:aca97dd11e3816f52fea1b6d1ef6ab182"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3f1b69b1c773f27b9177eccedefc70ce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a3f1b69b1c773f27b9177eccedefc70ce">XDPPSU_INTR_LIV_ABUF_UNDRFLW_MASK</a>&#160;&#160;&#160;0x00001000</td></tr>
<tr class="memdesc:a3f1b69b1c773f27b9177eccedefc70ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt asserted when live audio is enabled at subsystem, but the input does not match audio sample rate.  <a href="#a3f1b69b1c773f27b9177eccedefc70ce">More...</a><br/></td></tr>
<tr class="separator:a3f1b69b1c773f27b9177eccedefc70ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8818806e37ca6066c15b8c69360ae630"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a8818806e37ca6066c15b8c69360ae630">XDPPSU_INTR_VBLNK_START_MASK</a>&#160;&#160;&#160;0x00002000</td></tr>
<tr class="memdesc:a8818806e37ca6066c15b8c69360ae630"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt at start of early vertical blanking.  <a href="#a8818806e37ca6066c15b8c69360ae630">More...</a><br/></td></tr>
<tr class="separator:a8818806e37ca6066c15b8c69360ae630"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3bb90175ec9b586e94ec756c6ea1f4d6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a3bb90175ec9b586e94ec756c6ea1f4d6">XDPPSU_INTR_PIXEL1_MATCH_MASK</a>&#160;&#160;&#160;0x00004000</td></tr>
<tr class="memdesc:a3bb90175ec9b586e94ec756c6ea1f4d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">When VCOUNT and HCOUNT from AV buffer manager register 0x078 matches early VCOUNT.  <a href="#a3bb90175ec9b586e94ec756c6ea1f4d6">More...</a><br/></td></tr>
<tr class="separator:a3bb90175ec9b586e94ec756c6ea1f4d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac3e3297900544ef6e07f2f4327a92f92"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ac3e3297900544ef6e07f2f4327a92f92">XDPPSU_INTR_PIXEL0_MATCH_MASK</a>&#160;&#160;&#160;0x00008000</td></tr>
<tr class="memdesc:ac3e3297900544ef6e07f2f4327a92f92"><td class="mdescLeft">&#160;</td><td class="mdescRight">When VCOUNT and HCOUNT from AV buffer manager register 0x074 matches early VCOUNT.  <a href="#ac3e3297900544ef6e07f2f4327a92f92">More...</a><br/></td></tr>
<tr class="separator:ac3e3297900544ef6e07f2f4327a92f92"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1d8c73cf290587e5915d0c4e6049cb0a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a1d8c73cf290587e5915d0c4e6049cb0a">XDPPSU_INTR_CHBUF5_UNDERFLW_MASK</a>&#160;&#160;&#160;0x00010000</td></tr>
<tr class="memdesc:a1d8c73cf290587e5915d0c4e6049cb0a"><td class="mdescLeft">&#160;</td><td class="mdescRight">AV buffer manager channel buffer 5 underflow.  <a href="#a1d8c73cf290587e5915d0c4e6049cb0a">More...</a><br/></td></tr>
<tr class="separator:a1d8c73cf290587e5915d0c4e6049cb0a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a10c8cc1cb4610a2165ee38673b247d1b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a10c8cc1cb4610a2165ee38673b247d1b">XDPPSU_INTR_CHBUF4_UNDERFLW_MASK</a>&#160;&#160;&#160;0x00020000</td></tr>
<tr class="memdesc:a10c8cc1cb4610a2165ee38673b247d1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">AV buffer manager channel buffer 4 underflow.  <a href="#a10c8cc1cb4610a2165ee38673b247d1b">More...</a><br/></td></tr>
<tr class="separator:a10c8cc1cb4610a2165ee38673b247d1b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2cc02e429a27f26b8b5db19aeeabfdaf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a2cc02e429a27f26b8b5db19aeeabfdaf">XDPPSU_INTR_CHBUF3_UNDERFLW_MASK</a>&#160;&#160;&#160;0x00040000</td></tr>
<tr class="memdesc:a2cc02e429a27f26b8b5db19aeeabfdaf"><td class="mdescLeft">&#160;</td><td class="mdescRight">AV buffer manager channel buffer 3 underflow.  <a href="#a2cc02e429a27f26b8b5db19aeeabfdaf">More...</a><br/></td></tr>
<tr class="separator:a2cc02e429a27f26b8b5db19aeeabfdaf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad391bfc383276a337b92ee23c11677ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ad391bfc383276a337b92ee23c11677ad">XDPPSU_INTR_CHBUF2_UNDERFLW_MASK</a>&#160;&#160;&#160;0x00080000</td></tr>
<tr class="memdesc:ad391bfc383276a337b92ee23c11677ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">AV buffer manager channel buffer 2 underflow.  <a href="#ad391bfc383276a337b92ee23c11677ad">More...</a><br/></td></tr>
<tr class="separator:ad391bfc383276a337b92ee23c11677ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a29ec84c65e201cc8549a1b6c62959831"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a29ec84c65e201cc8549a1b6c62959831">XDPPSU_INTR_CHBUF1_UNDERFLW_MASK</a>&#160;&#160;&#160;0x00100000</td></tr>
<tr class="memdesc:a29ec84c65e201cc8549a1b6c62959831"><td class="mdescLeft">&#160;</td><td class="mdescRight">AV buffer manager channel buffer 1 underflow.  <a href="#a29ec84c65e201cc8549a1b6c62959831">More...</a><br/></td></tr>
<tr class="separator:a29ec84c65e201cc8549a1b6c62959831"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adb8065c93945e4783ae56e08b3832a5b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#adb8065c93945e4783ae56e08b3832a5b">XDPPSU_INTR_CHBUF0_UNDERFLW_MASK</a>&#160;&#160;&#160;0x00200000</td></tr>
<tr class="memdesc:adb8065c93945e4783ae56e08b3832a5b"><td class="mdescLeft">&#160;</td><td class="mdescRight">AV buffer manager channel buffer 0 underflow.  <a href="#adb8065c93945e4783ae56e08b3832a5b">More...</a><br/></td></tr>
<tr class="separator:adb8065c93945e4783ae56e08b3832a5b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac1d170e10ff34c6cac0a5a178f661776"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ac1d170e10ff34c6cac0a5a178f661776">XDPPSU_INTR_CHBUF5_OVERFLW_MASK</a>&#160;&#160;&#160;0x00400000</td></tr>
<tr class="memdesc:ac1d170e10ff34c6cac0a5a178f661776"><td class="mdescLeft">&#160;</td><td class="mdescRight">AV buffer manager channel buffer 5 overflow.  <a href="#ac1d170e10ff34c6cac0a5a178f661776">More...</a><br/></td></tr>
<tr class="separator:ac1d170e10ff34c6cac0a5a178f661776"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0d3f4391a441d40cef2419d2c0795dad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a0d3f4391a441d40cef2419d2c0795dad">XDPPSU_INTR_CHBUF4_OVERFLW_MASK</a>&#160;&#160;&#160;0x00800000</td></tr>
<tr class="memdesc:a0d3f4391a441d40cef2419d2c0795dad"><td class="mdescLeft">&#160;</td><td class="mdescRight">AV buffer manager channel buffer 4 overflow.  <a href="#a0d3f4391a441d40cef2419d2c0795dad">More...</a><br/></td></tr>
<tr class="separator:a0d3f4391a441d40cef2419d2c0795dad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7571f776db070b66f2f2a86308db39f0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a7571f776db070b66f2f2a86308db39f0">XDPPSU_INTR_CHBUF3_OVERFLW_MASK</a>&#160;&#160;&#160;0x01000000</td></tr>
<tr class="memdesc:a7571f776db070b66f2f2a86308db39f0"><td class="mdescLeft">&#160;</td><td class="mdescRight">AV buffer manager channel buffer 3 overflow.  <a href="#a7571f776db070b66f2f2a86308db39f0">More...</a><br/></td></tr>
<tr class="separator:a7571f776db070b66f2f2a86308db39f0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a39a9592b65b1635198bbde9e4adcab37"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a39a9592b65b1635198bbde9e4adcab37">XDPPSU_INTR_CHBUF2_OVERFLW_MASK</a>&#160;&#160;&#160;0x02000000</td></tr>
<tr class="memdesc:a39a9592b65b1635198bbde9e4adcab37"><td class="mdescLeft">&#160;</td><td class="mdescRight">AV buffer manager channel buffer 2 overflow.  <a href="#a39a9592b65b1635198bbde9e4adcab37">More...</a><br/></td></tr>
<tr class="separator:a39a9592b65b1635198bbde9e4adcab37"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8db1b3424e328e29cacea2334574dcb1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a8db1b3424e328e29cacea2334574dcb1">XDPPSU_INTR_CHBUF1_OVERFLW_MASK</a>&#160;&#160;&#160;0x04000000</td></tr>
<tr class="memdesc:a8db1b3424e328e29cacea2334574dcb1"><td class="mdescLeft">&#160;</td><td class="mdescRight">AV buffer manager channel buffer 1 overflow.  <a href="#a8db1b3424e328e29cacea2334574dcb1">More...</a><br/></td></tr>
<tr class="separator:a8db1b3424e328e29cacea2334574dcb1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad5113d356b9c8fd6267e021b75edd364"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ad5113d356b9c8fd6267e021b75edd364">XDPPSU_INTR_CHBUF0_OVERFLW_MASK</a>&#160;&#160;&#160;0x08000000</td></tr>
<tr class="memdesc:ad5113d356b9c8fd6267e021b75edd364"><td class="mdescLeft">&#160;</td><td class="mdescRight">AV buffer manager channel buffer 0 overflow.  <a href="#ad5113d356b9c8fd6267e021b75edd364">More...</a><br/></td></tr>
<tr class="separator:ad5113d356b9c8fd6267e021b75edd364"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a587a6015742d74938f7fe657fee359b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a587a6015742d74938f7fe657fee359b6">XDPPSU_INTR_CUST_TS_2_MASK</a>&#160;&#160;&#160;0x10000000</td></tr>
<tr class="memdesc:a587a6015742d74938f7fe657fee359b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Indicates that a user defined custom event 2 has triggered a timestamp.  <a href="#a587a6015742d74938f7fe657fee359b6">More...</a><br/></td></tr>
<tr class="separator:a587a6015742d74938f7fe657fee359b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abebc492322f633e84cdff5b1843759bb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#abebc492322f633e84cdff5b1843759bb">XDPPSU_INTR_CUST_TS_MASK</a>&#160;&#160;&#160;0x20000000</td></tr>
<tr class="memdesc:abebc492322f633e84cdff5b1843759bb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Indicates that a user defined custom event has triggered a timestamp.  <a href="#abebc492322f633e84cdff5b1843759bb">More...</a><br/></td></tr>
<tr class="separator:abebc492322f633e84cdff5b1843759bb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a258f7a242c29b8fb48a375501f9c6a38"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a258f7a242c29b8fb48a375501f9c6a38">XDPPSU_INTR_EXT_VSYNC_TS_MASK</a>&#160;&#160;&#160;0x40000000</td></tr>
<tr class="memdesc:a258f7a242c29b8fb48a375501f9c6a38"><td class="mdescLeft">&#160;</td><td class="mdescRight">Indicates that an external VSYNC has triggered a timestamp.  <a href="#a258f7a242c29b8fb48a375501f9c6a38">More...</a><br/></td></tr>
<tr class="separator:a258f7a242c29b8fb48a375501f9c6a38"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae000f500b8922ed564f17d073967bfe9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ae000f500b8922ed564f17d073967bfe9">XDPPSU_INTR_VSYNC_TS_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:ae000f500b8922ed564f17d073967bfe9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Indicates that a VSYNC timestamp is available.  <a href="#ae000f500b8922ed564f17d073967bfe9">More...</a><br/></td></tr>
<tr class="separator:ae000f500b8922ed564f17d073967bfe9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3a7707ccbeb559d57c0def91f0f49c43"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a3a7707ccbeb559d57c0def91f0f49c43">XDPPSU_SOFT_RESET_EN</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="memdesc:a3a7707ccbeb559d57c0def91f0f49c43"><td class="mdescLeft">&#160;</td><td class="mdescRight">Indicates that the soft reset has been set.  <a href="#a3a7707ccbeb559d57c0def91f0f49c43">More...</a><br/></td></tr>
<tr class="separator:a3a7707ccbeb559d57c0def91f0f49c43"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a96dd8a3fe382bc8e7ae78429c44b7d52"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#a96dd8a3fe382bc8e7ae78429c44b7d52">XDPPSU_DP_DISABLE</a>&#160;&#160;&#160;0x0</td></tr>
<tr class="memdesc:a96dd8a3fe382bc8e7ae78429c44b7d52"><td class="mdescLeft">&#160;</td><td class="mdescRight">This field disables the DisplayPort core.  <a href="#a96dd8a3fe382bc8e7ae78429c44b7d52">More...</a><br/></td></tr>
<tr class="separator:a96dd8a3fe382bc8e7ae78429c44b7d52"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab18f03371514f98187b96e9350c03816"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdppsu__hw_8h.html#ab18f03371514f98187b96e9350c03816">XDPPSU_DP_ENABLE</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="memdesc:ab18f03371514f98187b96e9350c03816"><td class="mdescLeft">&#160;</td><td class="mdescRight">This field enables the DisplayPort core.  <a href="#ab18f03371514f98187b96e9350c03816">More...</a><br/></td></tr>
<tr class="separator:ab18f03371514f98187b96e9350c03816"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Receiver capability field.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Address mapping for the DisplayPort Configuration Data (DPCD) of the downstream device. </p>
</div></td></tr>
<tr class="memitem:a3b8a9e5d7f67e6a3bc0c445bd68d64af"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3b8a9e5d7f67e6a3bc0c445bd68d64af"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_REV</b>&#160;&#160;&#160;0x00000</td></tr>
<tr class="separator:a3b8a9e5d7f67e6a3bc0c445bd68d64af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac2c217fb7f61869b0cc42f8c05f41a44"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac2c217fb7f61869b0cc42f8c05f41a44"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_MAX_LINK_RATE</b>&#160;&#160;&#160;0x00001</td></tr>
<tr class="separator:ac2c217fb7f61869b0cc42f8c05f41a44"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9f44c2f7301b7f8c3b0db43ce748c114"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9f44c2f7301b7f8c3b0db43ce748c114"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_MAX_LANE_COUNT</b>&#160;&#160;&#160;0x00002</td></tr>
<tr class="separator:a9f44c2f7301b7f8c3b0db43ce748c114"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af54f1021c977e158a3abeff30e4b8d8c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af54f1021c977e158a3abeff30e4b8d8c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_MAX_DOWNSPREAD</b>&#160;&#160;&#160;0x00003</td></tr>
<tr class="separator:af54f1021c977e158a3abeff30e4b8d8c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acff4337c63e71442b10cfb652dfa99e5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="acff4337c63e71442b10cfb652dfa99e5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_NORP_PWR_V_CAP</b>&#160;&#160;&#160;0x00004</td></tr>
<tr class="separator:acff4337c63e71442b10cfb652dfa99e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9c8b3d67c9585e7143a065a42ef7038d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9c8b3d67c9585e7143a065a42ef7038d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_PRESENT</b>&#160;&#160;&#160;0x00005</td></tr>
<tr class="separator:a9c8b3d67c9585e7143a065a42ef7038d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab4f0fbf3e36350c632354cb038e60dcc"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab4f0fbf3e36350c632354cb038e60dcc"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ML_CH_CODING_CAP</b>&#160;&#160;&#160;0x00006</td></tr>
<tr class="separator:ab4f0fbf3e36350c632354cb038e60dcc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7ab5ddb89242692cb3a988c38ad80fcb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7ab5ddb89242692cb3a988c38ad80fcb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_COUNT_MSA_OUI</b>&#160;&#160;&#160;0x00007</td></tr>
<tr class="separator:a7ab5ddb89242692cb3a988c38ad80fcb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1af0a05b0d895ea3356da2b765fa16e5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1af0a05b0d895ea3356da2b765fa16e5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_RX_PORT0_CAP_0</b>&#160;&#160;&#160;0x00008</td></tr>
<tr class="separator:a1af0a05b0d895ea3356da2b765fa16e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aace7a889e5d0f19ebf591f12a4ade019"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aace7a889e5d0f19ebf591f12a4ade019"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_RX_PORT0_CAP_1</b>&#160;&#160;&#160;0x00009</td></tr>
<tr class="separator:aace7a889e5d0f19ebf591f12a4ade019"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a646dbbd8fd468bf769b5bfe978640c66"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a646dbbd8fd468bf769b5bfe978640c66"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_RX_PORT1_CAP_0</b>&#160;&#160;&#160;0x0000A</td></tr>
<tr class="separator:a646dbbd8fd468bf769b5bfe978640c66"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0f2cf24a6c9b34d608a4da8c7fcca6a5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0f2cf24a6c9b34d608a4da8c7fcca6a5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_RX_PORT1_CAP_1</b>&#160;&#160;&#160;0x0000B</td></tr>
<tr class="separator:a0f2cf24a6c9b34d608a4da8c7fcca6a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac9c51eccd62dc5fae8db2eb15a8c7a9a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac9c51eccd62dc5fae8db2eb15a8c7a9a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_I2C_SPEED_CTL_CAP</b>&#160;&#160;&#160;0x0000C</td></tr>
<tr class="separator:ac9c51eccd62dc5fae8db2eb15a8c7a9a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae0f73ed4d68aac94f6e9fae8a0520109"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae0f73ed4d68aac94f6e9fae8a0520109"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_EDP_CFG_CAP</b>&#160;&#160;&#160;0x0000D</td></tr>
<tr class="separator:ae0f73ed4d68aac94f6e9fae8a0520109"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac0da48647d9f8f7c57ac1ed2fdda9dbd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac0da48647d9f8f7c57ac1ed2fdda9dbd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAIN_AUX_RD_INTERVAL</b>&#160;&#160;&#160;0x0000E</td></tr>
<tr class="separator:ac0da48647d9f8f7c57ac1ed2fdda9dbd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a321c6db841e7d1035c969e17a44be2b1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a321c6db841e7d1035c969e17a44be2b1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ADAPTER_CAP</b>&#160;&#160;&#160;0x0000F</td></tr>
<tr class="separator:a321c6db841e7d1035c969e17a44be2b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4838585a40884bd4ed6f2aed852c4b78"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4838585a40884bd4ed6f2aed852c4b78"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_FAUX_CAP</b>&#160;&#160;&#160;0x00020</td></tr>
<tr class="separator:a4838585a40884bd4ed6f2aed852c4b78"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a98a7910c7d91327e8d11d9327536d94f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a98a7910c7d91327e8d11d9327536d94f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_MSTM_CAP</b>&#160;&#160;&#160;0x00021</td></tr>
<tr class="separator:a98a7910c7d91327e8d11d9327536d94f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac46c241c962622bd0bdbac60c2251c8f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac46c241c962622bd0bdbac60c2251c8f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_NUM_AUDIO_EPS</b>&#160;&#160;&#160;0x00022</td></tr>
<tr class="separator:ac46c241c962622bd0bdbac60c2251c8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acd43ad593ceff3b029c2e02af1670f34"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="acd43ad593ceff3b029c2e02af1670f34"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_AV_GRANULARITY</b>&#160;&#160;&#160;0x00023</td></tr>
<tr class="separator:acd43ad593ceff3b029c2e02af1670f34"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a04fd93ea998d499bc837b59455c081cd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a04fd93ea998d499bc837b59455c081cd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_AUD_DEC_LAT_7_0</b>&#160;&#160;&#160;0x00024</td></tr>
<tr class="separator:a04fd93ea998d499bc837b59455c081cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a51cc1777123224d55282ac8d105ce364"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a51cc1777123224d55282ac8d105ce364"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_AUD_DEC_LAT_15_8</b>&#160;&#160;&#160;0x00025</td></tr>
<tr class="separator:a51cc1777123224d55282ac8d105ce364"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a76e777317e18fb07af886e000ca0c832"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a76e777317e18fb07af886e000ca0c832"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_AUD_PP_LAT_7_0</b>&#160;&#160;&#160;0x00026</td></tr>
<tr class="separator:a76e777317e18fb07af886e000ca0c832"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6937a65f5d73937cd652ed8e54d6343c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6937a65f5d73937cd652ed8e54d6343c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_AUD_PP_LAT_15_8</b>&#160;&#160;&#160;0x00027</td></tr>
<tr class="separator:a6937a65f5d73937cd652ed8e54d6343c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae03d1c5d85fb4d7efacf6350c71ab74b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae03d1c5d85fb4d7efacf6350c71ab74b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_VID_INTER_LAT</b>&#160;&#160;&#160;0x00028</td></tr>
<tr class="separator:ae03d1c5d85fb4d7efacf6350c71ab74b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ada1600e876720e76be105d4c701aeecc"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ada1600e876720e76be105d4c701aeecc"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_VID_PROG_LAT</b>&#160;&#160;&#160;0x00029</td></tr>
<tr class="separator:ada1600e876720e76be105d4c701aeecc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:addc79185710cf50866c5b5c758204959"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="addc79185710cf50866c5b5c758204959"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_REP_LAT</b>&#160;&#160;&#160;0x0002A</td></tr>
<tr class="separator:addc79185710cf50866c5b5c758204959"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a05150b06dbc467974a8e7885eeef70d2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a05150b06dbc467974a8e7885eeef70d2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_AUD_DEL_INS_7_0</b>&#160;&#160;&#160;0x0002B</td></tr>
<tr class="separator:a05150b06dbc467974a8e7885eeef70d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac5623183da805d9e69bbc66a1b17fc00"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac5623183da805d9e69bbc66a1b17fc00"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_AUD_DEL_INS_15_8</b>&#160;&#160;&#160;0x0002C</td></tr>
<tr class="separator:ac5623183da805d9e69bbc66a1b17fc00"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9275c6fa3c97b0169236cd348fa0d420"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9275c6fa3c97b0169236cd348fa0d420"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_AUD_DEL_INS_23_16</b>&#160;&#160;&#160;0x0002D</td></tr>
<tr class="separator:a9275c6fa3c97b0169236cd348fa0d420"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0e9a745e69ca02828585dad49415efb4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0e9a745e69ca02828585dad49415efb4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_GUID</b>&#160;&#160;&#160;0x00030</td></tr>
<tr class="separator:a0e9a745e69ca02828585dad49415efb4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aacf3ffb2343cf7808dd258217715faf2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aacf3ffb2343cf7808dd258217715faf2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_RX_GTC_VALUE_7_0</b>&#160;&#160;&#160;0x00054</td></tr>
<tr class="separator:aacf3ffb2343cf7808dd258217715faf2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a52fb97ce2e6413feef0e458c72826692"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a52fb97ce2e6413feef0e458c72826692"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_RX_GTC_VALUE_15_8</b>&#160;&#160;&#160;0x00055</td></tr>
<tr class="separator:a52fb97ce2e6413feef0e458c72826692"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae2b9fabbdf3922feb5c0ef344ad0b715"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae2b9fabbdf3922feb5c0ef344ad0b715"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_RX_GTC_VALUE_23_16</b>&#160;&#160;&#160;0x00056</td></tr>
<tr class="separator:ae2b9fabbdf3922feb5c0ef344ad0b715"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a078e89919fa314a4f48e54df64fcfe4f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a078e89919fa314a4f48e54df64fcfe4f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_RX_GTC_VALUE_31_24</b>&#160;&#160;&#160;0x00057</td></tr>
<tr class="separator:a078e89919fa314a4f48e54df64fcfe4f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7c9e4ab04195ec4ce3982681ec734751"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7c9e4ab04195ec4ce3982681ec734751"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_RX_GTC_MSTR_REQ</b>&#160;&#160;&#160;0x00058</td></tr>
<tr class="separator:a7c9e4ab04195ec4ce3982681ec734751"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac79962fe7db243443addce75b3f1ef89"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac79962fe7db243443addce75b3f1ef89"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_RX_GTC_FREQ_LOCK_DONE</b>&#160;&#160;&#160;0x00059</td></tr>
<tr class="separator:ac79962fe7db243443addce75b3f1ef89"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa245756e17f61d73f53881f0bad7b481"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa245756e17f61d73f53881f0bad7b481"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_0_CAP</b>&#160;&#160;&#160;0x00080</td></tr>
<tr class="separator:aa245756e17f61d73f53881f0bad7b481"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2eb4309c0d0a4049f1f414929e54c637"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2eb4309c0d0a4049f1f414929e54c637"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_1_CAP</b>&#160;&#160;&#160;0x00081</td></tr>
<tr class="separator:a2eb4309c0d0a4049f1f414929e54c637"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad668b8c8b91645769e3301fbd26908a8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad668b8c8b91645769e3301fbd26908a8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_2_CAP</b>&#160;&#160;&#160;0x00082</td></tr>
<tr class="separator:ad668b8c8b91645769e3301fbd26908a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a80462f89866b9a7ccf71e699d7fa3d0e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a80462f89866b9a7ccf71e699d7fa3d0e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_3_CAP</b>&#160;&#160;&#160;0x00083</td></tr>
<tr class="separator:a80462f89866b9a7ccf71e699d7fa3d0e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5457a70b4ddd7f17a48461812f8d28c1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5457a70b4ddd7f17a48461812f8d28c1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_0_DET_CAP</b>&#160;&#160;&#160;0x00080</td></tr>
<tr class="separator:a5457a70b4ddd7f17a48461812f8d28c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aaaa6a2edbc8eea544fa239e9cedc3023"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aaaa6a2edbc8eea544fa239e9cedc3023"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_1_DET_CAP</b>&#160;&#160;&#160;0x00084</td></tr>
<tr class="separator:aaaa6a2edbc8eea544fa239e9cedc3023"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae4d9380c4be5753f9bb55b5041427bd6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae4d9380c4be5753f9bb55b5041427bd6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_2_DET_CAP</b>&#160;&#160;&#160;0x00088</td></tr>
<tr class="separator:ae4d9380c4be5753f9bb55b5041427bd6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1235a54b5bc139e91870e1499d907cf4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1235a54b5bc139e91870e1499d907cf4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_3_DET_CAP</b>&#160;&#160;&#160;0x0008C</td></tr>
<tr class="separator:a1235a54b5bc139e91870e1499d907cf4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Link configuration field.</div></td></tr>
<tr class="memitem:af7c666754a0097f06b0efbdff248140f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af7c666754a0097f06b0efbdff248140f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LINK_BW_SET</b>&#160;&#160;&#160;0x00100</td></tr>
<tr class="separator:af7c666754a0097f06b0efbdff248140f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa0a145cd7da8f6ade40df9de89c77996"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa0a145cd7da8f6ade40df9de89c77996"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LANE_COUNT_SET</b>&#160;&#160;&#160;0x00101</td></tr>
<tr class="separator:aa0a145cd7da8f6ade40df9de89c77996"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9faaa18f63a53422c1d3586eb03e6aa2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9faaa18f63a53422c1d3586eb03e6aa2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TP_SET</b>&#160;&#160;&#160;0x00102</td></tr>
<tr class="separator:a9faaa18f63a53422c1d3586eb03e6aa2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abbb3b23a230cdd531e1d8acade2ee627"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abbb3b23a230cdd531e1d8acade2ee627"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAINING_LANE0_SET</b>&#160;&#160;&#160;0x00103</td></tr>
<tr class="separator:abbb3b23a230cdd531e1d8acade2ee627"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:affc510105fa1f79ea4115329abb6f751"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="affc510105fa1f79ea4115329abb6f751"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAINING_LANE1_SET</b>&#160;&#160;&#160;0x00104</td></tr>
<tr class="separator:affc510105fa1f79ea4115329abb6f751"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a44bed5b85cafc82b84a746deacf8d7cb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a44bed5b85cafc82b84a746deacf8d7cb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAINING_LANE2_SET</b>&#160;&#160;&#160;0x00105</td></tr>
<tr class="separator:a44bed5b85cafc82b84a746deacf8d7cb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab575d97c14adaa7d9a23ffee13af5acf"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab575d97c14adaa7d9a23ffee13af5acf"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAINING_LANE3_SET</b>&#160;&#160;&#160;0x00106</td></tr>
<tr class="separator:ab575d97c14adaa7d9a23ffee13af5acf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a39b4befb8948a8187afa8cb5071fc7a4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a39b4befb8948a8187afa8cb5071fc7a4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSPREAD_CTRL</b>&#160;&#160;&#160;0x00107</td></tr>
<tr class="separator:a39b4befb8948a8187afa8cb5071fc7a4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a75618d5ed5ec099d5aa68a38063888a7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a75618d5ed5ec099d5aa68a38063888a7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ML_CH_CODING_SET</b>&#160;&#160;&#160;0x00108</td></tr>
<tr class="separator:a75618d5ed5ec099d5aa68a38063888a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7e7fd75838f13fe395edcc89a1e5eb6e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7e7fd75838f13fe395edcc89a1e5eb6e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_I2C_SPEED_CTL_SET</b>&#160;&#160;&#160;0x00109</td></tr>
<tr class="separator:a7e7fd75838f13fe395edcc89a1e5eb6e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8f46258d87062e7dd3d7abc51554b6d7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8f46258d87062e7dd3d7abc51554b6d7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_EDP_CFG_SET</b>&#160;&#160;&#160;0x0010A</td></tr>
<tr class="separator:a8f46258d87062e7dd3d7abc51554b6d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9df69e7cccb0c272e533add06b0de3a5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9df69e7cccb0c272e533add06b0de3a5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LINK_QUAL_LANE0_SET</b>&#160;&#160;&#160;0x0010B</td></tr>
<tr class="separator:a9df69e7cccb0c272e533add06b0de3a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a13f9c6344dc16841f7116358627b968d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a13f9c6344dc16841f7116358627b968d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LINK_QUAL_LANE1_SET</b>&#160;&#160;&#160;0x0010C</td></tr>
<tr class="separator:a13f9c6344dc16841f7116358627b968d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a41be73b1528066855b00fedd8d0185d6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a41be73b1528066855b00fedd8d0185d6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LINK_QUAL_LANE2_SET</b>&#160;&#160;&#160;0x0010D</td></tr>
<tr class="separator:a41be73b1528066855b00fedd8d0185d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7e6ad205951da9c6dbe0ce40a9a9018e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7e6ad205951da9c6dbe0ce40a9a9018e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LINK_QUAL_LANE3_SET</b>&#160;&#160;&#160;0x0010E</td></tr>
<tr class="separator:a7e6ad205951da9c6dbe0ce40a9a9018e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abc4f1620e0e4e3f6b1d2736b2dcbcb78"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abc4f1620e0e4e3f6b1d2736b2dcbcb78"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAINING_LANE0_1_SET2</b>&#160;&#160;&#160;0x0010F</td></tr>
<tr class="separator:abc4f1620e0e4e3f6b1d2736b2dcbcb78"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab15a574c56ee71e625425679be72dea1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab15a574c56ee71e625425679be72dea1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAINING_LANE2_3_SET2</b>&#160;&#160;&#160;0x00110</td></tr>
<tr class="separator:ab15a574c56ee71e625425679be72dea1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2e43407c19b683726a54ec3b69992825"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2e43407c19b683726a54ec3b69992825"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_MSTM_CTRL</b>&#160;&#160;&#160;0x00111</td></tr>
<tr class="separator:a2e43407c19b683726a54ec3b69992825"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4b58b891650dc5dd8e9990288bc5cfb0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4b58b891650dc5dd8e9990288bc5cfb0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_AUDIO_DELAY_7_0</b>&#160;&#160;&#160;0x00112</td></tr>
<tr class="separator:a4b58b891650dc5dd8e9990288bc5cfb0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a617b302d23c796e4207c9bc5c12f7d20"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a617b302d23c796e4207c9bc5c12f7d20"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_AUDIO_DELAY_15_8</b>&#160;&#160;&#160;0x00113</td></tr>
<tr class="separator:a617b302d23c796e4207c9bc5c12f7d20"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ada10538f8158fbc04d4ba1c85a5b365e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ada10538f8158fbc04d4ba1c85a5b365e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_AUDIO_DELAY_23_6</b>&#160;&#160;&#160;0x00114</td></tr>
<tr class="separator:ada10538f8158fbc04d4ba1c85a5b365e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a25abb986832947b44fb1bc1cbbeee296"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a25abb986832947b44fb1bc1cbbeee296"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_UPSTREAM_DEVICE_DP_PWR_NEED</b>&#160;&#160;&#160;0x00118</td></tr>
<tr class="separator:a25abb986832947b44fb1bc1cbbeee296"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af235ecfd0fecc358e6b83b24f55c5fdd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af235ecfd0fecc358e6b83b24f55c5fdd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_FAUX_MODE_CTRL</b>&#160;&#160;&#160;0x00120</td></tr>
<tr class="separator:af235ecfd0fecc358e6b83b24f55c5fdd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a09da3bf205365a29e09e643800319f97"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a09da3bf205365a29e09e643800319f97"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_FAUX_FORWARD_CH_DRIVE_SET</b>&#160;&#160;&#160;0x00121</td></tr>
<tr class="separator:a09da3bf205365a29e09e643800319f97"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a81fda6f2f5416f6ceb3eebb8cce7a413"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a81fda6f2f5416f6ceb3eebb8cce7a413"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_BACK_CH_STATUS</b>&#160;&#160;&#160;0x00122</td></tr>
<tr class="separator:a81fda6f2f5416f6ceb3eebb8cce7a413"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab5fbb47b5448a0796b1b5819d1fb0c8d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab5fbb47b5448a0796b1b5819d1fb0c8d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT</b>&#160;&#160;&#160;0x00123</td></tr>
<tr class="separator:ab5fbb47b5448a0796b1b5819d1fb0c8d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a060d7a8edc0b7f119964e8ef997edf49"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a060d7a8edc0b7f119964e8ef997edf49"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME</b>&#160;&#160;&#160;0x00125</td></tr>
<tr class="separator:a060d7a8edc0b7f119964e8ef997edf49"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae95a9d437101b8acc406b6c918ea0512"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae95a9d437101b8acc406b6c918ea0512"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TX_GTC_VALUE_7_0</b>&#160;&#160;&#160;0x00154</td></tr>
<tr class="separator:ae95a9d437101b8acc406b6c918ea0512"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8cbae8991a040ecd6788a370ef63348e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8cbae8991a040ecd6788a370ef63348e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TX_GTC_VALUE_15_8</b>&#160;&#160;&#160;0x00155</td></tr>
<tr class="separator:a8cbae8991a040ecd6788a370ef63348e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a50859de7bb9d623b8b694034b2f82c0a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a50859de7bb9d623b8b694034b2f82c0a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TX_GTC_VALUE_23_16</b>&#160;&#160;&#160;0x00156</td></tr>
<tr class="separator:a50859de7bb9d623b8b694034b2f82c0a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a063d0c529ce0608b353c09140150fccd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a063d0c529ce0608b353c09140150fccd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TX_GTC_VALUE_31_24</b>&#160;&#160;&#160;0x00157</td></tr>
<tr class="separator:a063d0c529ce0608b353c09140150fccd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aff6c56efc6966bda7486fa1eb3e046c1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aff6c56efc6966bda7486fa1eb3e046c1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_RX_GTC_VALUE_PHASE_SKEW_EN</b>&#160;&#160;&#160;0x00158</td></tr>
<tr class="separator:aff6c56efc6966bda7486fa1eb3e046c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a10d6849bda7fff9e0c348fd8f948a8a4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a10d6849bda7fff9e0c348fd8f948a8a4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TX_GTC_FREQ_LOCK_DONE</b>&#160;&#160;&#160;0x00159</td></tr>
<tr class="separator:a10d6849bda7fff9e0c348fd8f948a8a4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa029615cf3184cecd6e4b8066afc69bf"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa029615cf3184cecd6e4b8066afc69bf"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ADAPTER_CTRL</b>&#160;&#160;&#160;0x001A0</td></tr>
<tr class="separator:aa029615cf3184cecd6e4b8066afc69bf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a91b9ba2213d8402790027be78ff3e9d4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a91b9ba2213d8402790027be78ff3e9d4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_BRANCH_DEVICE_CTRL</b>&#160;&#160;&#160;0x001A1</td></tr>
<tr class="separator:a91b9ba2213d8402790027be78ff3e9d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad6de00edfb30147facef2eb6824921a4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad6de00edfb30147facef2eb6824921a4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_PAYLOAD_ALLOCATE_SET</b>&#160;&#160;&#160;0x001C0</td></tr>
<tr class="separator:ad6de00edfb30147facef2eb6824921a4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad4b9db1a7a371e6399d9fcd75e0c914e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad4b9db1a7a371e6399d9fcd75e0c914e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT</b>&#160;&#160;&#160;0x001C1</td></tr>
<tr class="separator:ad4b9db1a7a371e6399d9fcd75e0c914e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aada6644a5b61d7db5dbfe208a1606869"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aada6644a5b61d7db5dbfe208a1606869"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT</b>&#160;&#160;&#160;0x001C2</td></tr>
<tr class="separator:aada6644a5b61d7db5dbfe208a1606869"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Link/sink status field.</div></td></tr>
<tr class="memitem:a4d19651a6dbc5a1df1aa2327ee22ba36"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4d19651a6dbc5a1df1aa2327ee22ba36"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SINK_COUNT</b>&#160;&#160;&#160;0x00200</td></tr>
<tr class="separator:a4d19651a6dbc5a1df1aa2327ee22ba36"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0e0e3683d9c5b6132186a23a2e8200c4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0e0e3683d9c5b6132186a23a2e8200c4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DEVICE_SERVICE_IRQ</b>&#160;&#160;&#160;0x00201</td></tr>
<tr class="separator:a0e0e3683d9c5b6132186a23a2e8200c4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a16cf720e6161a9300f1ae6c247650396"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a16cf720e6161a9300f1ae6c247650396"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_STATUS_LANE_0_1</b>&#160;&#160;&#160;0x00202</td></tr>
<tr class="separator:a16cf720e6161a9300f1ae6c247650396"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae68ddc6709a09336eabfc6d5ddce5c61"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae68ddc6709a09336eabfc6d5ddce5c61"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_STATUS_LANE_2_3</b>&#160;&#160;&#160;0x00203</td></tr>
<tr class="separator:ae68ddc6709a09336eabfc6d5ddce5c61"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad159d270500cad248c92d41fc3402cbf"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad159d270500cad248c92d41fc3402cbf"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LANE_ALIGN_STATUS_UPDATED</b>&#160;&#160;&#160;0x00204</td></tr>
<tr class="separator:ad159d270500cad248c92d41fc3402cbf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8f71c9d9fc69bc4863ff360ba19e24d0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8f71c9d9fc69bc4863ff360ba19e24d0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SINK_STATUS</b>&#160;&#160;&#160;0x00205</td></tr>
<tr class="separator:a8f71c9d9fc69bc4863ff360ba19e24d0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7d8964143d636522b2404a3d3a49458f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7d8964143d636522b2404a3d3a49458f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ADJ_REQ_LANE_0_1</b>&#160;&#160;&#160;0x00206</td></tr>
<tr class="separator:a7d8964143d636522b2404a3d3a49458f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a11d2e24d620d5b79b946048f8f7568ac"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a11d2e24d620d5b79b946048f8f7568ac"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ADJ_REQ_LANE_2_3</b>&#160;&#160;&#160;0x00207</td></tr>
<tr class="separator:a11d2e24d620d5b79b946048f8f7568ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a85d9a335e2408ed59c04f3013b85504a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a85d9a335e2408ed59c04f3013b85504a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAINING_SCORE_LANE_0</b>&#160;&#160;&#160;0x00208</td></tr>
<tr class="separator:a85d9a335e2408ed59c04f3013b85504a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0208afe3635de906f8c85c695980ca72"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0208afe3635de906f8c85c695980ca72"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAINING_SCORE_LANE_1</b>&#160;&#160;&#160;0x00209</td></tr>
<tr class="separator:a0208afe3635de906f8c85c695980ca72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6843f6a2e871a364fafd5eb85e7001f0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6843f6a2e871a364fafd5eb85e7001f0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAINING_SCORE_LANE_2</b>&#160;&#160;&#160;0x0020A</td></tr>
<tr class="separator:a6843f6a2e871a364fafd5eb85e7001f0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a87422d0a7576e3aabdf7f5130b0d17a2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a87422d0a7576e3aabdf7f5130b0d17a2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAINING_SCORE_LANE_3</b>&#160;&#160;&#160;0x0020B</td></tr>
<tr class="separator:a87422d0a7576e3aabdf7f5130b0d17a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a95d21125dd85467ac37f318ce2b56b96"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a95d21125dd85467ac37f318ce2b56b96"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ADJ_REQ_PC2</b>&#160;&#160;&#160;0x0020C</td></tr>
<tr class="separator:a95d21125dd85467ac37f318ce2b56b96"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a453a7b4eadc6ac3f45278dc01d0923d1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a453a7b4eadc6ac3f45278dc01d0923d1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT</b>&#160;&#160;&#160;0x0020D</td></tr>
<tr class="separator:a453a7b4eadc6ac3f45278dc01d0923d1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac4f264a5456d3b302329002f797bee8a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac4f264a5456d3b302329002f797bee8a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SYMBOL_ERROR_COUNT_LANE_0</b>&#160;&#160;&#160;0x00210</td></tr>
<tr class="separator:ac4f264a5456d3b302329002f797bee8a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4ecd7548d5c0f617828be5f609308de4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4ecd7548d5c0f617828be5f609308de4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SYMBOL_ERROR_COUNT_LANE_1</b>&#160;&#160;&#160;0x00212</td></tr>
<tr class="separator:a4ecd7548d5c0f617828be5f609308de4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae44fe3b5e79fa70365949b893623a0ed"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae44fe3b5e79fa70365949b893623a0ed"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SYMBOL_ERROR_COUNT_LANE_2</b>&#160;&#160;&#160;0x00214</td></tr>
<tr class="separator:ae44fe3b5e79fa70365949b893623a0ed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad60590b39c2ef5cb59f9efac99586761"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad60590b39c2ef5cb59f9efac99586761"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SYMBOL_ERROR_COUNT_LANE_3</b>&#160;&#160;&#160;0x00216</td></tr>
<tr class="separator:ad60590b39c2ef5cb59f9efac99586761"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Automated testing sub-field.</div></td></tr>
<tr class="memitem:a1bb59b04cb4571831364c68e40420654"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1bb59b04cb4571831364c68e40420654"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_FAUX_FORWARD_CH_STATUS</b>&#160;&#160;&#160;0x00280</td></tr>
<tr class="separator:a1bb59b04cb4571831364c68e40420654"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a323da6a1a0e10def9b61db5f4da0dc2b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a323da6a1a0e10def9b61db5f4da0dc2b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_FAUX_BACK_CH_DRIVE_SET</b>&#160;&#160;&#160;0x00281</td></tr>
<tr class="separator:a323da6a1a0e10def9b61db5f4da0dc2b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a048edbbe03fb2384966624f6b75e508d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a048edbbe03fb2384966624f6b75e508d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL</b>&#160;&#160;&#160;0x00282</td></tr>
<tr class="separator:a048edbbe03fb2384966624f6b75e508d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa8271e8372847256be3372ecc97af035"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa8271e8372847256be3372ecc97af035"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_PAYLOAD_TABLE_UPDATE_STATUS</b>&#160;&#160;&#160;0x002C0</td></tr>
<tr class="separator:aa8271e8372847256be3372ecc97af035"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aac80e3399a233befece6897366880bf8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aac80e3399a233befece6897366880bf8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_VC_PAYLOAD_ID_SLOT</b>(SlotNum)&#160;&#160;&#160;(XDPPSU_DPCD_PAYLOAD_TABLE_UPDATE_STATUS + SlotNum)</td></tr>
<tr class="separator:aac80e3399a233befece6897366880bf8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Sink control field.</div></td></tr>
<tr class="memitem:a29ae58033ca84d25db7b29f91e00335b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a29ae58033ca84d25db7b29f91e00335b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SET_POWER_DP_PWR_VOLTAGE</b>&#160;&#160;&#160;0x00600</td></tr>
<tr class="separator:a29ae58033ca84d25db7b29f91e00335b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Sideband message buffers.</div></td></tr>
<tr class="memitem:a3edd2f385438f3b2d97b36a4255065ad"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3edd2f385438f3b2d97b36a4255065ad"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWN_REQ</b>&#160;&#160;&#160;0x01000</td></tr>
<tr class="separator:a3edd2f385438f3b2d97b36a4255065ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a59b14f130bee0bc13003f3955bfeab27"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a59b14f130bee0bc13003f3955bfeab27"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_UP_REP</b>&#160;&#160;&#160;0x01200</td></tr>
<tr class="separator:a59b14f130bee0bc13003f3955bfeab27"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a83528b1472ede4f6c0430d2dafcaf38a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a83528b1472ede4f6c0430d2dafcaf38a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWN_REP</b>&#160;&#160;&#160;0x01400</td></tr>
<tr class="separator:a83528b1472ede4f6c0430d2dafcaf38a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2a84f9d7cc5ce10dc9a0731ddf151ca0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2a84f9d7cc5ce10dc9a0731ddf151ca0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_UP_REQ</b>&#160;&#160;&#160;0x01600</td></tr>
<tr class="separator:a2a84f9d7cc5ce10dc9a0731ddf151ca0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Event status indicator field.</div></td></tr>
<tr class="memitem:af4fef6c9bd119c19182492f29572386a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af4fef6c9bd119c19182492f29572386a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SINK_COUNT_ESI</b>&#160;&#160;&#160;0x02002</td></tr>
<tr class="separator:af4fef6c9bd119c19182492f29572386a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa82f4e3785ec636f414c432cf06ec0d3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa82f4e3785ec636f414c432cf06ec0d3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0</b>&#160;&#160;&#160;0x02003</td></tr>
<tr class="separator:aa82f4e3785ec636f414c432cf06ec0d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6039e7632da68dac5368d67d8e097589"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6039e7632da68dac5368d67d8e097589"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1</b>&#160;&#160;&#160;0x02004</td></tr>
<tr class="separator:a6039e7632da68dac5368d67d8e097589"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac0b95470118ebadf6976717442df39a8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac0b95470118ebadf6976717442df39a8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0</b>&#160;&#160;&#160;0x02005</td></tr>
<tr class="separator:ac0b95470118ebadf6976717442df39a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad3cb28bf4f37859dbd965c5549d80d6a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad3cb28bf4f37859dbd965c5549d80d6a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SINK_LANE0_1_STATUS</b>&#160;&#160;&#160;0x0200C</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SINK_LANE2_3_STATUS</b>&#160;&#160;&#160;0x0200D</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SINK_ALIGN_STATUS_UPDATED_ESI</b>&#160;&#160;&#160;0x0200E</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SINK_STATUS_ESI</b>&#160;&#160;&#160;0x0200F</td></tr>
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<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Field addresses and sizes.</div></td></tr>
<tr class="memitem:aee5e535cbc464ff73d3151bc08512bb5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aee5e535cbc464ff73d3151bc08512bb5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_RECEIVER_CAP_FIELD_START</b>&#160;&#160;&#160;XDPPSU_DPCD_REV</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_RECEIVER_CAP_FIELD_SIZE</b>&#160;&#160;&#160;0x100</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LINK_CFG_FIELD_START</b>&#160;&#160;&#160;XDPPSU_DPCD_LINK_BW_SET</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LINK_CFG_FIELD_SIZE</b>&#160;&#160;&#160;0x100</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LINK_SINK_STATUS_FIELD_START</b>&#160;&#160;&#160;XDPPSU_DPCD_SINK_COUNT</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LINK_SINK_STATUS_FIELD_SIZE</b>&#160;&#160;&#160;0x17</td></tr>
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<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Receiver capability field masks,</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>shifts, and register values. </p>
</div></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_REV_MNR_MASK</b>&#160;&#160;&#160;0x0F</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_REV_MJR_MASK</b>&#160;&#160;&#160;0xF0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_REV_MJR_SHIFT</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_MAX_LINK_RATE_162GBPS</b>&#160;&#160;&#160;0x06</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_MAX_LINK_RATE_270GBPS</b>&#160;&#160;&#160;0x0A</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_MAX_LINK_RATE_540GBPS</b>&#160;&#160;&#160;0x14</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_MAX_LANE_COUNT_MASK</b>&#160;&#160;&#160;0x1F</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_MAX_LANE_COUNT_1</b>&#160;&#160;&#160;0x01</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_MAX_LANE_COUNT_2</b>&#160;&#160;&#160;0x02</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_MAX_LANE_COUNT_4</b>&#160;&#160;&#160;0x04</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TPS3_SUPPORT_MASK</b>&#160;&#160;&#160;0x40</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ENHANCED_FRAME_SUPPORT_MASK</b>&#160;&#160;&#160;0x80</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_MAX_DOWNSPREAD_MASK</b>&#160;&#160;&#160;0x01</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK</b>&#160;&#160;&#160;0x40</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_PRESENT_MASK</b>&#160;&#160;&#160;0x01</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_TYPE_MASK</b>&#160;&#160;&#160;0x06</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_TYPE_SHIFT</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_TYPE_DP</b>&#160;&#160;&#160;0x0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_TYPE_AVGA_ADVII</b>&#160;&#160;&#160;0x1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP</b>&#160;&#160;&#160;0x2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_TYPE_OTHERS</b>&#160;&#160;&#160;0x3</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_FORMAT_CONV_MASK</b>&#160;&#160;&#160;0x08</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK</b>&#160;&#160;&#160;0x10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ML_CH_CODING_MASK</b>&#160;&#160;&#160;0x01</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_COUNT_MASK</b>&#160;&#160;&#160;0x0F</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_MSA_TIMING_PAR_IGNORED_MASK</b>&#160;&#160;&#160;0x40</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_OUI_SUPPORT_MASK</b>&#160;&#160;&#160;0x80</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK</b>&#160;&#160;&#160;0x02</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK</b>&#160;&#160;&#160;0x04</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_I2C_SPEED_CTL_NONE</b>&#160;&#160;&#160;0x00</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_I2C_SPEED_CTL_1KBIPS</b>&#160;&#160;&#160;0x01</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_I2C_SPEED_CTL_5KBIPS</b>&#160;&#160;&#160;0x02</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_I2C_SPEED_CTL_10KBIPS</b>&#160;&#160;&#160;0x04</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_I2C_SPEED_CTL_100KBIPS</b>&#160;&#160;&#160;0x08</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_I2C_SPEED_CTL_400KBIPS</b>&#160;&#160;&#160;0x10</td></tr>
<tr class="separator:ae46a686b5222918850981b51d700dd2a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a10e7e0d80ae29498f1e102ba6e3aae3f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a10e7e0d80ae29498f1e102ba6e3aae3f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_I2C_SPEED_CTL_1MBIPS</b>&#160;&#160;&#160;0x20</td></tr>
<tr class="separator:a10e7e0d80ae29498f1e102ba6e3aae3f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a17e5212578ad7e355f5050d012f4cfa4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a17e5212578ad7e355f5050d012f4cfa4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAIN_AUX_RD_INT_100_400US</b>&#160;&#160;&#160;0x00</td></tr>
<tr class="separator:a17e5212578ad7e355f5050d012f4cfa4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab48162de8d28d37f0dad37f3413dd556"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab48162de8d28d37f0dad37f3413dd556"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAIN_AUX_RD_INT_4MS</b>&#160;&#160;&#160;0x01</td></tr>
<tr class="separator:ab48162de8d28d37f0dad37f3413dd556"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a23ac47c4c0dc1cf636bceb707f7a2f2b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a23ac47c4c0dc1cf636bceb707f7a2f2b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAIN_AUX_RD_INT_8MS</b>&#160;&#160;&#160;0x02</td></tr>
<tr class="separator:a23ac47c4c0dc1cf636bceb707f7a2f2b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af0fadcaa206c6c0cf3e304ed178e6a37"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af0fadcaa206c6c0cf3e304ed178e6a37"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAIN_AUX_RD_INT_12MS</b>&#160;&#160;&#160;0x03</td></tr>
<tr class="separator:af0fadcaa206c6c0cf3e304ed178e6a37"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab1ef9348fc1efcf0588f8bfa17177963"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab1ef9348fc1efcf0588f8bfa17177963"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAIN_AUX_RD_INT_16MS</b>&#160;&#160;&#160;0x04</td></tr>
<tr class="separator:ab1ef9348fc1efcf0588f8bfa17177963"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1a85fbf6f4df066cac38d67f20bb6122"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1a85fbf6f4df066cac38d67f20bb6122"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_FAUX_CAP_MASK</b>&#160;&#160;&#160;0x01</td></tr>
<tr class="separator:a1a85fbf6f4df066cac38d67f20bb6122"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa9e7eeb998e927ef9d33122025ca2f51"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa9e7eeb998e927ef9d33122025ca2f51"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_MST_CAP_MASK</b>&#160;&#160;&#160;0x01</td></tr>
<tr class="separator:aa9e7eeb998e927ef9d33122025ca2f51"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3aac8d057e9b6269165de71d0cff643e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3aac8d057e9b6269165de71d0cff643e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_CAP_TYPE_MASK</b>&#160;&#160;&#160;0x07</td></tr>
<tr class="separator:a3aac8d057e9b6269165de71d0cff643e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a68d27dfea21b886ebf669de5b02609a3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a68d27dfea21b886ebf669de5b02609a3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_CAP_TYPE_DP</b>&#160;&#160;&#160;0x0</td></tr>
<tr class="separator:a68d27dfea21b886ebf669de5b02609a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aefadc0acef8fbf839fae5e42d7f60359"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aefadc0acef8fbf839fae5e42d7f60359"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_CAP_TYPE_AVGA</b>&#160;&#160;&#160;0x1</td></tr>
<tr class="separator:aefadc0acef8fbf839fae5e42d7f60359"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aeb47ad8cfebd5dcc127ad93759fe2495"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aeb47ad8cfebd5dcc127ad93759fe2495"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_CAP_TYPE_DVI</b>&#160;&#160;&#160;0x2</td></tr>
<tr class="separator:aeb47ad8cfebd5dcc127ad93759fe2495"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a467ac4ce8e24f14cea4873bd5e821607"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a467ac4ce8e24f14cea4873bd5e821607"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_CAP_TYPE_HDMI</b>&#160;&#160;&#160;0x3</td></tr>
<tr class="separator:a467ac4ce8e24f14cea4873bd5e821607"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad5db9847de6d6ca170c1b9379ba05ffb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad5db9847de6d6ca170c1b9379ba05ffb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_CAP_TYPE_OTHERS</b>&#160;&#160;&#160;0x4</td></tr>
<tr class="separator:ad5db9847de6d6ca170c1b9379ba05ffb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a67d99e2c1ba8fbec4e40aca46a541325"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a67d99e2c1ba8fbec4e40aca46a541325"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_CAP_TYPE_DPPP</b>&#160;&#160;&#160;0x5</td></tr>
<tr class="separator:a67d99e2c1ba8fbec4e40aca46a541325"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a13dd0040afd372e84785b3009912f8e9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a13dd0040afd372e84785b3009912f8e9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_CAP_HPD_MASK</b>&#160;&#160;&#160;0x80</td></tr>
<tr class="separator:a13dd0040afd372e84785b3009912f8e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a42b5c62e945fd7aed546b131647de3dd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a42b5c62e945fd7aed546b131647de3dd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK</b>&#160;&#160;&#160;0xF0</td></tr>
<tr class="separator:a42b5c62e945fd7aed546b131647de3dd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a193bd127526275678a86bd7005743e84"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a193bd127526275678a86bd7005743e84"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT</b>&#160;&#160;&#160;4</td></tr>
<tr class="separator:a193bd127526275678a86bd7005743e84"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1ef67ab3c6cb479a91c4ce63c73dcdc8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1ef67ab3c6cb479a91c4ce63c73dcdc8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60</b>&#160;&#160;&#160;0x1</td></tr>
<tr class="separator:a1ef67ab3c6cb479a91c4ce63c73dcdc8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a155eab8041fa634be8e5090d99d2f6ea"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a155eab8041fa634be8e5090d99d2f6ea"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50</b>&#160;&#160;&#160;0x2</td></tr>
<tr class="separator:a155eab8041fa634be8e5090d99d2f6ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af586b1e4f4da32fd19fbb3c19492b2de"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af586b1e4f4da32fd19fbb3c19492b2de"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60</b>&#160;&#160;&#160;0x3</td></tr>
<tr class="separator:af586b1e4f4da32fd19fbb3c19492b2de"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a98a113f1e90e4fda8cc57e2d2da1e1a3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a98a113f1e90e4fda8cc57e2d2da1e1a3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50</b>&#160;&#160;&#160;0x4</td></tr>
<tr class="separator:a98a113f1e90e4fda8cc57e2d2da1e1a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abc8c1cd101a4f048b3b26b626b5ae7d7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abc8c1cd101a4f048b3b26b626b5ae7d7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60</b>&#160;&#160;&#160;0x5</td></tr>
<tr class="separator:abc8c1cd101a4f048b3b26b626b5ae7d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:add918d8a39288a298efe29875ff16223"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="add918d8a39288a298efe29875ff16223"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50</b>&#160;&#160;&#160;0x7</td></tr>
<tr class="separator:add918d8a39288a298efe29875ff16223"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a40ba2031a890ed72836c8578a12433ca"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a40ba2031a890ed72836c8578a12433ca"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK</b>&#160;&#160;&#160;0x03</td></tr>
<tr class="separator:a40ba2031a890ed72836c8578a12433ca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aff997066c9142e65839aeb4e8e4170ae"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aff997066c9142e65839aeb4e8e4170ae"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_DCAP_MAX_BPC_8</b>&#160;&#160;&#160;0x0</td></tr>
<tr class="separator:aff997066c9142e65839aeb4e8e4170ae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8734477e2f3e1fc5c3e543a6fe77a7f8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8734477e2f3e1fc5c3e543a6fe77a7f8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_DCAP_MAX_BPC_10</b>&#160;&#160;&#160;0x1</td></tr>
<tr class="separator:a8734477e2f3e1fc5c3e543a6fe77a7f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a88fe9b90eeb8177e3112c1fb7e6355b3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a88fe9b90eeb8177e3112c1fb7e6355b3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_DCAP_MAX_BPC_12</b>&#160;&#160;&#160;0x2</td></tr>
<tr class="separator:a88fe9b90eeb8177e3112c1fb7e6355b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af19e37b141f60f44d1921b77cc979a51"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af19e37b141f60f44d1921b77cc979a51"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_DCAP_MAX_BPC_16</b>&#160;&#160;&#160;0x3</td></tr>
<tr class="separator:af19e37b141f60f44d1921b77cc979a51"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a38119d0e21a0579ebbd6e79bc70c9763"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a38119d0e21a0579ebbd6e79bc70c9763"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK</b>&#160;&#160;&#160;0x01</td></tr>
<tr class="separator:a38119d0e21a0579ebbd6e79bc70c9763"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae29f48367a03a0c644bccb058ebca5f7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae29f48367a03a0c644bccb058ebca5f7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_DCAP_DVI_DL_MASK</b>&#160;&#160;&#160;0x02</td></tr>
<tr class="separator:ae29f48367a03a0c644bccb058ebca5f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8067a49a03da0d0ab8cb3ae78ef8c5a3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8067a49a03da0d0ab8cb3ae78ef8c5a3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK</b>&#160;&#160;&#160;0x04</td></tr>
<tr class="separator:a8067a49a03da0d0ab8cb3ae78ef8c5a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Link configuration field masks,</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>shifts, and register values. </p>
</div></td></tr>
<tr class="memitem:ac7bcc9bf5ff1882b9af2afb9f79af519"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac7bcc9bf5ff1882b9af2afb9f79af519"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LINK_BW_SET_162GBPS</b>&#160;&#160;&#160;0x06</td></tr>
<tr class="separator:ac7bcc9bf5ff1882b9af2afb9f79af519"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac51edb6f513fca798fbd2ff82d6d68ba"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac51edb6f513fca798fbd2ff82d6d68ba"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LINK_BW_SET_270GBPS</b>&#160;&#160;&#160;0x0A</td></tr>
<tr class="separator:ac51edb6f513fca798fbd2ff82d6d68ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3e87ed97e8049796aaed406ac546f88b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3e87ed97e8049796aaed406ac546f88b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LINK_BW_SET_540GBPS</b>&#160;&#160;&#160;0x14</td></tr>
<tr class="separator:a3e87ed97e8049796aaed406ac546f88b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adf5f46d0f3ec39a1aa4c77d0ebed382c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="adf5f46d0f3ec39a1aa4c77d0ebed382c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LANE_COUNT_SET_MASK</b>&#160;&#160;&#160;0x1F</td></tr>
<tr class="separator:adf5f46d0f3ec39a1aa4c77d0ebed382c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4e765a5d7c4119265af959cfcf35525a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4e765a5d7c4119265af959cfcf35525a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LANE_COUNT_SET_1</b>&#160;&#160;&#160;0x01</td></tr>
<tr class="separator:a4e765a5d7c4119265af959cfcf35525a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aea080b4201e0f66d63baa3ebfe925bbf"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aea080b4201e0f66d63baa3ebfe925bbf"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LANE_COUNT_SET_2</b>&#160;&#160;&#160;0x02</td></tr>
<tr class="separator:aea080b4201e0f66d63baa3ebfe925bbf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a64f56c9bbc5b2d48e4e9c6f658e325f4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a64f56c9bbc5b2d48e4e9c6f658e325f4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LANE_COUNT_SET_4</b>&#160;&#160;&#160;0x04</td></tr>
<tr class="separator:a64f56c9bbc5b2d48e4e9c6f658e325f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4ce690d96b0fdd938c63563ce091a748"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4ce690d96b0fdd938c63563ce091a748"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ENHANCED_FRAME_EN_MASK</b>&#160;&#160;&#160;0x80</td></tr>
<tr class="separator:a4ce690d96b0fdd938c63563ce091a748"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a60228627d2f2d8191f0082cca9e27b42"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a60228627d2f2d8191f0082cca9e27b42"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TP_SEL_MASK</b>&#160;&#160;&#160;0x03</td></tr>
<tr class="separator:a60228627d2f2d8191f0082cca9e27b42"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac7259a6015c015a4dc6da69f47097868"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac7259a6015c015a4dc6da69f47097868"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TP_SEL_OFF</b>&#160;&#160;&#160;0x0</td></tr>
<tr class="separator:ac7259a6015c015a4dc6da69f47097868"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0e36021d44d6243ec9c59dae5b5e82a8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0e36021d44d6243ec9c59dae5b5e82a8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TP_SEL_TP1</b>&#160;&#160;&#160;0x1</td></tr>
<tr class="separator:a0e36021d44d6243ec9c59dae5b5e82a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a047465c154b13f4dfb4fe93d855f82a1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a047465c154b13f4dfb4fe93d855f82a1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TP_SEL_TP2</b>&#160;&#160;&#160;0x2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TP_SEL_TP3</b>&#160;&#160;&#160;0x3</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TP_SET_LQP_MASK</b>&#160;&#160;&#160;0x06</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TP_SET_LQP_SHIFT</b>&#160;&#160;&#160;2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TP_SET_LQP_OFF</b>&#160;&#160;&#160;0x0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TP_SET_LQP_D102_TEST</b>&#160;&#160;&#160;0x1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TP_SET_LQP_SER_MES</b>&#160;&#160;&#160;0x2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TP_SET_LQP_PRBS7</b>&#160;&#160;&#160;0x3</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TP_SET_REC_CLK_OUT_EN_MASK</b>&#160;&#160;&#160;0x10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TP_SET_SCRAMB_DIS_MASK</b>&#160;&#160;&#160;0x20</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TP_SET_SE_COUNT_SEL_MASK</b>&#160;&#160;&#160;0xC0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TP_SET_SE_COUNT_SEL_SHIFT</b>&#160;&#160;&#160;6</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TP_SET_SE_COUNT_SEL_DE_ISE</b>&#160;&#160;&#160;0x0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TP_SET_SE_COUNT_SEL_DE</b>&#160;&#160;&#160;0x1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TP_SET_SE_COUNT_SEL_ISE</b>&#160;&#160;&#160;0x2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAINING_LANEX_SET_VS_MASK</b>&#160;&#160;&#160;0x03</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK</b>&#160;&#160;&#160;0x04</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAINING_LANEX_SET_PE_MASK</b>&#160;&#160;&#160;0x18</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAINING_LANEX_SET_PE_SHIFT</b>&#160;&#160;&#160;3</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK</b>&#160;&#160;&#160;0x20</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SPREAD_AMP_MASK</b>&#160;&#160;&#160;0x10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK</b>&#160;&#160;&#160;0x80</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAINING_LANE_0_2_SET_PC2_MASK</b>&#160;&#160;&#160;0x03</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK</b>&#160;&#160;&#160;0x04</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAINING_LANE_1_3_SET_PC2_MASK</b>&#160;&#160;&#160;0x30</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK</b>&#160;&#160;&#160;0x40</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_MST_EN_MASK</b>&#160;&#160;&#160;0x01</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_UP_REQ_EN_MASK</b>&#160;&#160;&#160;0x02</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_UP_IS_SRC_MASK</b>&#160;&#160;&#160;0x03</td></tr>
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<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Link/sink status field masks, shifts,</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>and register values. </p>
</div></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SINK_COUNT_LOW_MASK</b>&#160;&#160;&#160;0x3F</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SINK_CP_READY_MASK</b>&#160;&#160;&#160;0x40</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SINK_COUNT_HIGH_MASK</b>&#160;&#160;&#160;0x80</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SINK_COUNT_HIGH_LOW_SHIFT</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_STATUS_LANE_0_CR_DONE_MASK</b>&#160;&#160;&#160;0x01</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_STATUS_LANE_0_CE_DONE_MASK</b>&#160;&#160;&#160;0x02</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_STATUS_LANE_0_SL_DONE_MASK</b>&#160;&#160;&#160;0x04</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_STATUS_LANE_1_CR_DONE_MASK</b>&#160;&#160;&#160;0x10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_STATUS_LANE_1_CE_DONE_MASK</b>&#160;&#160;&#160;0x20</td></tr>
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<tr class="memitem:a366c221c0e334e75b8124cd1e2ee3e7c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a366c221c0e334e75b8124cd1e2ee3e7c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_STATUS_LANE_1_SL_DONE_MASK</b>&#160;&#160;&#160;0x40</td></tr>
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<tr class="memitem:af504aecd9d7a3dd892179bf5d8b5462e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af504aecd9d7a3dd892179bf5d8b5462e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_STATUS_LANE_2_CR_DONE_MASK</b>&#160;&#160;&#160;0x01</td></tr>
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<tr class="memitem:a1dbb1b99ca8b05b988da38eaa505e54a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1dbb1b99ca8b05b988da38eaa505e54a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_STATUS_LANE_2_CE_DONE_MASK</b>&#160;&#160;&#160;0x02</td></tr>
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<tr class="memitem:a31d5a348be5bed1ff7a30712c318f7be"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a31d5a348be5bed1ff7a30712c318f7be"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_STATUS_LANE_2_SL_DONE_MASK</b>&#160;&#160;&#160;0x04</td></tr>
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<tr class="memitem:a1a73164b14e0a40173cdf8f448528c41"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1a73164b14e0a40173cdf8f448528c41"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_STATUS_LANE_3_CR_DONE_MASK</b>&#160;&#160;&#160;0x10</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_STATUS_LANE_3_CE_DONE_MASK</b>&#160;&#160;&#160;0x20</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_STATUS_LANE_3_SL_DONE_MASK</b>&#160;&#160;&#160;0x40</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK</b>&#160;&#160;&#160;0x01</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK</b>&#160;&#160;&#160;0x40</td></tr>
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<tr class="memitem:a27cb4792ea4bc9e07bd948d35d4e0766"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a27cb4792ea4bc9e07bd948d35d4e0766"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK</b>&#160;&#160;&#160;0x80</td></tr>
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<tr class="memitem:aac36e17609e4c87448f76f574f4c5e54"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aac36e17609e4c87448f76f574f4c5e54"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK</b>&#160;&#160;&#160;0x01</td></tr>
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<tr class="memitem:a6123eca7d3eadb9eb79bba1997e69dd8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6123eca7d3eadb9eb79bba1997e69dd8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK</b>&#160;&#160;&#160;0x02</td></tr>
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<tr class="memitem:af61f536f1df13a2b11ff1e161487cb21"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af61f536f1df13a2b11ff1e161487cb21"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ADJ_REQ_LANE_0_2_VS_MASK</b>&#160;&#160;&#160;0x03</td></tr>
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<tr class="memitem:ad2101082edb04ec579488ac72e30af49"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad2101082edb04ec579488ac72e30af49"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ADJ_REQ_LANE_0_2_PE_MASK</b>&#160;&#160;&#160;0x0C</td></tr>
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<tr class="memitem:a5730660055c31c9f0979edeaf9e78385"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5730660055c31c9f0979edeaf9e78385"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT</b>&#160;&#160;&#160;2</td></tr>
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<tr class="memitem:a66254c65f7aa563498c933f062f5e1e5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a66254c65f7aa563498c933f062f5e1e5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ADJ_REQ_LANE_1_3_VS_MASK</b>&#160;&#160;&#160;0x30</td></tr>
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<tr class="memitem:a9a58ea57cc2d81a170e61329ed39f72a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9a58ea57cc2d81a170e61329ed39f72a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT</b>&#160;&#160;&#160;4</td></tr>
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<tr class="memitem:aef46014505a3838be574db62ad962f69"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aef46014505a3838be574db62ad962f69"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ADJ_REQ_LANE_1_3_PE_MASK</b>&#160;&#160;&#160;0xC0</td></tr>
<tr class="separator:aef46014505a3838be574db62ad962f69"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a71f5779ed880e0f0fc0683fbe2429ee0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a71f5779ed880e0f0fc0683fbe2429ee0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT</b>&#160;&#160;&#160;6</td></tr>
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<tr class="memitem:a935307084ad1d9087caacf81e8ec2a66"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a935307084ad1d9087caacf81e8ec2a66"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ADJ_REQ_PC2_LANE_0_MASK</b>&#160;&#160;&#160;0x03</td></tr>
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<tr class="memitem:af6713dc266c2f70b5f2b11b91a6b4941"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af6713dc266c2f70b5f2b11b91a6b4941"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ADJ_REQ_PC2_LANE_1_MASK</b>&#160;&#160;&#160;0x0C</td></tr>
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<tr class="memitem:ac8c2eb14b8d652a73d79af51328d0259"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac8c2eb14b8d652a73d79af51328d0259"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ADJ_REQ_PC2_LANE_1_SHIFT</b>&#160;&#160;&#160;2</td></tr>
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<tr class="memitem:ac733755fdab8a1be2c0c40c23af130db"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac733755fdab8a1be2c0c40c23af130db"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ADJ_REQ_PC2_LANE_2_MASK</b>&#160;&#160;&#160;0x30</td></tr>
<tr class="separator:ac733755fdab8a1be2c0c40c23af130db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afe473c3a0fb1bfffd4a9fa2c70c6bdd2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="afe473c3a0fb1bfffd4a9fa2c70c6bdd2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ADJ_REQ_PC2_LANE_2_SHIFT</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ADJ_REQ_PC2_LANE_3_MASK</b>&#160;&#160;&#160;0xC0</td></tr>
<tr class="separator:a8d1a20eef9313753f2593b21f07fee3f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a49ee4b0539a77b55392cc8c4c033c266"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a49ee4b0539a77b55392cc8c4c033c266"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DPCD_ADJ_REQ_PC2_LANE_3_SHIFT</b>&#160;&#160;&#160;6</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Extended Display Identification Data: Field addresses and sizes.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Address mapping for the Extended Display Identification Data (EDID) of the downstream device. </p>
</div></td></tr>
<tr class="memitem:a62b0ef64f46a3984a8f7380ff68c9d11"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a62b0ef64f46a3984a8f7380ff68c9d11"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_SEGPTR_ADDR</b>&#160;&#160;&#160;0x30</td></tr>
<tr class="separator:a62b0ef64f46a3984a8f7380ff68c9d11"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a19b07be8cd27a1eb239ea57b3dae4f6e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a19b07be8cd27a1eb239ea57b3dae4f6e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_ADDR</b>&#160;&#160;&#160;0x50</td></tr>
<tr class="separator:a19b07be8cd27a1eb239ea57b3dae4f6e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af7ebae28f103ad6d907064cf5f349823"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af7ebae28f103ad6d907064cf5f349823"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_BLOCK_SIZE</b>&#160;&#160;&#160;128</td></tr>
<tr class="separator:af7ebae28f103ad6d907064cf5f349823"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9e8333fe61a2744660f5175e18e41dfe"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9e8333fe61a2744660f5175e18e41dfe"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_DD</b>(Num)&#160;&#160;&#160;(0x36 + (18 * Num))</td></tr>
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<tr class="memitem:afd1d466522e57a73b534899f7586c59a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="afd1d466522e57a73b534899f7586c59a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_PTM</b>&#160;&#160;&#160;XDPPSU_EDID_DTD_DD(0)</td></tr>
<tr class="separator:afd1d466522e57a73b534899f7586c59a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2b14c5b690a09754f4d43ec783192fae"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2b14c5b690a09754f4d43ec783192fae"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_EXT_BLOCK_COUNT</b>&#160;&#160;&#160;0x7E</td></tr>
<tr class="separator:a2b14c5b690a09754f4d43ec783192fae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Extended Display Identification Data: Register offsets for the</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Tiled Display Topology (TDT) section data block. </p>
</div></td></tr>
<tr class="memitem:a388960bb0484f245d1cafb93631194a1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a388960bb0484f245d1cafb93631194a1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_PIXEL_CLK_KHZ_LSB</b>&#160;&#160;&#160;0x00</td></tr>
<tr class="separator:a388960bb0484f245d1cafb93631194a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa0d32f8887b40d181b91fa542a720539"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa0d32f8887b40d181b91fa542a720539"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_PIXEL_CLK_KHZ_MSB</b>&#160;&#160;&#160;0x01</td></tr>
<tr class="separator:aa0d32f8887b40d181b91fa542a720539"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab61aace8765046981b7cebfbb068deb4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab61aace8765046981b7cebfbb068deb4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_HRES_LSB</b>&#160;&#160;&#160;0x02</td></tr>
<tr class="separator:ab61aace8765046981b7cebfbb068deb4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8a57552f029b3006ba34f9fcd2a6453c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8a57552f029b3006ba34f9fcd2a6453c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_HBLANK_LSB</b>&#160;&#160;&#160;0x03</td></tr>
<tr class="separator:a8a57552f029b3006ba34f9fcd2a6453c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5a44e692fc769b1e1a4ad9a0e0a450c3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5a44e692fc769b1e1a4ad9a0e0a450c3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_HRES_HBLANK_U4</b>&#160;&#160;&#160;0x04</td></tr>
<tr class="separator:a5a44e692fc769b1e1a4ad9a0e0a450c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa34c79c1250a92e71375804a4e3f3c57"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa34c79c1250a92e71375804a4e3f3c57"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_VRES_LSB</b>&#160;&#160;&#160;0x05</td></tr>
<tr class="separator:aa34c79c1250a92e71375804a4e3f3c57"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab7e937415ba06b0db0ca2150954556b7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab7e937415ba06b0db0ca2150954556b7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_VBLANK_LSB</b>&#160;&#160;&#160;0x06</td></tr>
<tr class="separator:ab7e937415ba06b0db0ca2150954556b7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ade102d00139081334b382fba0dfe497e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ade102d00139081334b382fba0dfe497e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_VRES_VBLANK_U4</b>&#160;&#160;&#160;0x07</td></tr>
<tr class="separator:ade102d00139081334b382fba0dfe497e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a16d222cf874750cc267acb038c5b6519"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a16d222cf874750cc267acb038c5b6519"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_HFPORCH_LSB</b>&#160;&#160;&#160;0x08</td></tr>
<tr class="separator:a16d222cf874750cc267acb038c5b6519"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af31dbbcf037e0a2d42bb373b2f44a3b8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af31dbbcf037e0a2d42bb373b2f44a3b8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_HSPW_LSB</b>&#160;&#160;&#160;0x09</td></tr>
<tr class="separator:af31dbbcf037e0a2d42bb373b2f44a3b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afa1674259d72b0c308ca16000e6dd836"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="afa1674259d72b0c308ca16000e6dd836"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_VFPORCH_VSPW_L4</b>&#160;&#160;&#160;0x0A</td></tr>
<tr class="separator:afa1674259d72b0c308ca16000e6dd836"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aea9ea2425237b33de8a56d893cded134"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aea9ea2425237b33de8a56d893cded134"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_XFPORCH_XSPW_U2</b>&#160;&#160;&#160;0x0B</td></tr>
<tr class="separator:aea9ea2425237b33de8a56d893cded134"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad60ecc2e1f3ad78a21054c50016634ed"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad60ecc2e1f3ad78a21054c50016634ed"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_HIMGSIZE_MM_LSB</b>&#160;&#160;&#160;0x0C</td></tr>
<tr class="separator:ad60ecc2e1f3ad78a21054c50016634ed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5ac5a16f8b7daee3b56236ab4be92053"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5ac5a16f8b7daee3b56236ab4be92053"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_VIMGSIZE_MM_LSB</b>&#160;&#160;&#160;0x0D</td></tr>
<tr class="separator:a5ac5a16f8b7daee3b56236ab4be92053"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad05842883494a1a53240f4ea04524df8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad05842883494a1a53240f4ea04524df8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_XIMGSIZE_MM_U4</b>&#160;&#160;&#160;0x0E</td></tr>
<tr class="separator:ad05842883494a1a53240f4ea04524df8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a68ac3ce79987631fcbaa279ff23592ab"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a68ac3ce79987631fcbaa279ff23592ab"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_HBORDER</b>&#160;&#160;&#160;0x0F</td></tr>
<tr class="separator:a68ac3ce79987631fcbaa279ff23592ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a05a72356b71eea9c041753892563e049"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a05a72356b71eea9c041753892563e049"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_VBORDER</b>&#160;&#160;&#160;0x10</td></tr>
<tr class="separator:a05a72356b71eea9c041753892563e049"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac4681047d9b1d8f1a2080e85803b19ef"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac4681047d9b1d8f1a2080e85803b19ef"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_SIGNAL</b>&#160;&#160;&#160;0x11</td></tr>
<tr class="separator:ac4681047d9b1d8f1a2080e85803b19ef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4086584899f6dbad206dbc971d661ce9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4086584899f6dbad206dbc971d661ce9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_EXT_BLOCK_TAG</b>&#160;&#160;&#160;0x00</td></tr>
<tr class="separator:a4086584899f6dbad206dbc971d661ce9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a96ab361b716fbb8c68d046288c9b35a7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a96ab361b716fbb8c68d046288c9b35a7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_VER_REV</b>&#160;&#160;&#160;0x00</td></tr>
<tr class="separator:a96ab361b716fbb8c68d046288c9b35a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6950c14d81ffbc66b64befedd74bf6e8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6950c14d81ffbc66b64befedd74bf6e8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_SIZE</b>&#160;&#160;&#160;0x01</td></tr>
<tr class="separator:a6950c14d81ffbc66b64befedd74bf6e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4f0228dfdd4030788158fdca88141fec"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4f0228dfdd4030788158fdca88141fec"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TYPE</b>&#160;&#160;&#160;0x02</td></tr>
<tr class="separator:a4f0228dfdd4030788158fdca88141fec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a47784ed8a58fa628ac489c4271d9186a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a47784ed8a58fa628ac489c4271d9186a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_EXT_COUNT</b>&#160;&#160;&#160;0x03</td></tr>
<tr class="separator:a47784ed8a58fa628ac489c4271d9186a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a89494a7972b214e2f063ce983c7bab5e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a89494a7972b214e2f063ce983c7bab5e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_PAYLOAD_START</b>&#160;&#160;&#160;0x04</td></tr>
<tr class="separator:a89494a7972b214e2f063ce983c7bab5e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a05c83aa91e1158fc111daf19023d04da"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a05c83aa91e1158fc111daf19023d04da"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_DB_SEC_TAG</b>&#160;&#160;&#160;0x00</td></tr>
<tr class="separator:a05c83aa91e1158fc111daf19023d04da"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a92bb81b022c9d0ea1b48ba1e82cf94b9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a92bb81b022c9d0ea1b48ba1e82cf94b9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_DB_SEC_REV</b>&#160;&#160;&#160;0x01</td></tr>
<tr class="separator:a92bb81b022c9d0ea1b48ba1e82cf94b9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab14b5c6f56e2134340b43c471d9ddbdb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab14b5c6f56e2134340b43c471d9ddbdb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_DB_SEC_SIZE</b>&#160;&#160;&#160;0x02</td></tr>
<tr class="separator:ab14b5c6f56e2134340b43c471d9ddbdb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acb5a0fd9e7af10ebd1cf6c25f2baa7f1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="acb5a0fd9e7af10ebd1cf6c25f2baa7f1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_TOP0</b>&#160;&#160;&#160;0x04</td></tr>
<tr class="separator:acb5a0fd9e7af10ebd1cf6c25f2baa7f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0af8406947acf1607972608d7aec022f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0af8406947acf1607972608d7aec022f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_TOP1</b>&#160;&#160;&#160;0x05</td></tr>
<tr class="separator:a0af8406947acf1607972608d7aec022f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a25ae72bf836956acae3ef29e7ceaa0c7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a25ae72bf836956acae3ef29e7ceaa0c7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_TOP2</b>&#160;&#160;&#160;0x06</td></tr>
<tr class="separator:a25ae72bf836956acae3ef29e7ceaa0c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a27a4888002c5a149e88d97e2bdd0e876"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a27a4888002c5a149e88d97e2bdd0e876"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_HSIZE0</b>&#160;&#160;&#160;0x07</td></tr>
<tr class="separator:a27a4888002c5a149e88d97e2bdd0e876"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abd884d5e39c6d79448f9cb5dd2463ef0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abd884d5e39c6d79448f9cb5dd2463ef0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_HSIZE1</b>&#160;&#160;&#160;0x08</td></tr>
<tr class="separator:abd884d5e39c6d79448f9cb5dd2463ef0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0d5c526353ec305829ef850e79ed02ba"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0d5c526353ec305829ef850e79ed02ba"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_VSIZE0</b>&#160;&#160;&#160;0x09</td></tr>
<tr class="separator:a0d5c526353ec305829ef850e79ed02ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae419baa604da23a12fb1589f90abf187"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae419baa604da23a12fb1589f90abf187"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_VSIZE1</b>&#160;&#160;&#160;0x0A</td></tr>
<tr class="separator:ae419baa604da23a12fb1589f90abf187"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae0078937982085d58c421733db3465c1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae0078937982085d58c421733db3465c1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_VENID0</b>&#160;&#160;&#160;0x10</td></tr>
<tr class="separator:ae0078937982085d58c421733db3465c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac23a1aeeae371ca49f210a24e721075d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac23a1aeeae371ca49f210a24e721075d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_VENID1</b>&#160;&#160;&#160;0x11</td></tr>
<tr class="separator:ac23a1aeeae371ca49f210a24e721075d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab48e76b7f16ef40ade5bfa8bfe21f508"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab48e76b7f16ef40ade5bfa8bfe21f508"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_VENID2</b>&#160;&#160;&#160;0x12</td></tr>
<tr class="separator:ab48e76b7f16ef40ade5bfa8bfe21f508"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8b8a9a67464d9fa6c913b979b468c9fa"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8b8a9a67464d9fa6c913b979b468c9fa"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_PCODE0</b>&#160;&#160;&#160;0x13</td></tr>
<tr class="separator:a8b8a9a67464d9fa6c913b979b468c9fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6db3fed15c4533fba789c85024d41413"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6db3fed15c4533fba789c85024d41413"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_PCODE1</b>&#160;&#160;&#160;0x14</td></tr>
<tr class="separator:a6db3fed15c4533fba789c85024d41413"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9ea5acc2f157dc91ea39a3683aee6a17"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9ea5acc2f157dc91ea39a3683aee6a17"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_SN0</b>&#160;&#160;&#160;0x15</td></tr>
<tr class="separator:a9ea5acc2f157dc91ea39a3683aee6a17"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a03ccec6415b14aebff3566e955e27db7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a03ccec6415b14aebff3566e955e27db7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_SN1</b>&#160;&#160;&#160;0x16</td></tr>
<tr class="separator:a03ccec6415b14aebff3566e955e27db7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4ba2b2cf15ba24310948241947dbb825"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4ba2b2cf15ba24310948241947dbb825"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_SN2</b>&#160;&#160;&#160;0x17</td></tr>
<tr class="separator:a4ba2b2cf15ba24310948241947dbb825"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afcc607435d70dd03687ec58e9485f256"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="afcc607435d70dd03687ec58e9485f256"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_SN3</b>&#160;&#160;&#160;0x18</td></tr>
<tr class="separator:afcc607435d70dd03687ec58e9485f256"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Extended Display Identification Data: Masks, shifts, and register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>values for the Tiled Display Topology (TDT) section data block. </p>
</div></td></tr>
<tr class="memitem:a7850af532d13979a1c32705f9fc8ff63"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7850af532d13979a1c32705f9fc8ff63"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK</b>&#160;&#160;&#160;0x0F</td></tr>
<tr class="separator:a7850af532d13979a1c32705f9fc8ff63"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ace82398ca2620a8ab0c2a2af6615c1d6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ace82398ca2620a8ab0c2a2af6615c1d6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_XRES_XBLANK_U4_XRES_MASK</b>&#160;&#160;&#160;0xF0</td></tr>
<tr class="separator:ace82398ca2620a8ab0c2a2af6615c1d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab64eda52fa626f4cb430be2c4ca695ab"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab64eda52fa626f4cb430be2c4ca695ab"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT</b>&#160;&#160;&#160;4</td></tr>
<tr class="separator:ab64eda52fa626f4cb430be2c4ca695ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a37aa4cc44cb52b66016753c512ffd976"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a37aa4cc44cb52b66016753c512ffd976"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK</b>&#160;&#160;&#160;0x0F</td></tr>
<tr class="separator:a37aa4cc44cb52b66016753c512ffd976"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a697e147ac0d41fe88af7b6c009389a60"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a697e147ac0d41fe88af7b6c009389a60"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK</b>&#160;&#160;&#160;0xF0</td></tr>
<tr class="separator:a697e147ac0d41fe88af7b6c009389a60"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aadcbe87ead2bb47ce3ec940a7c679769"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aadcbe87ead2bb47ce3ec940a7c679769"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT</b>&#160;&#160;&#160;4</td></tr>
<tr class="separator:aadcbe87ead2bb47ce3ec940a7c679769"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae9b258fbe9841fe7f38b1fe7ad5c5ffd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae9b258fbe9841fe7f38b1fe7ad5c5ffd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK</b>&#160;&#160;&#160;0xC0</td></tr>
<tr class="separator:ae9b258fbe9841fe7f38b1fe7ad5c5ffd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae8936e7c2cafe014fd65ac3f5d80a918"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae8936e7c2cafe014fd65ac3f5d80a918"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK</b>&#160;&#160;&#160;0x30</td></tr>
<tr class="separator:ae8936e7c2cafe014fd65ac3f5d80a918"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab7ee35449af46ee38974f736cd183baf"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab7ee35449af46ee38974f736cd183baf"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK</b>&#160;&#160;&#160;0x0C</td></tr>
<tr class="separator:ab7ee35449af46ee38974f736cd183baf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ada00a17f75d394c1031be20df3fa186e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ada00a17f75d394c1031be20df3fa186e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK</b>&#160;&#160;&#160;0x03</td></tr>
<tr class="separator:ada00a17f75d394c1031be20df3fa186e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6aede5689521c6a0cd4f1d5a8e140758"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6aede5689521c6a0cd4f1d5a8e140758"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT</b>&#160;&#160;&#160;6</td></tr>
<tr class="separator:a6aede5689521c6a0cd4f1d5a8e140758"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7da8ccea377ba1028485e0242dac1605"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7da8ccea377ba1028485e0242dac1605"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT</b>&#160;&#160;&#160;4</td></tr>
<tr class="separator:a7da8ccea377ba1028485e0242dac1605"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a27271abe3ee6cd79b56c0f7c478b7dbe"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a27271abe3ee6cd79b56c0f7c478b7dbe"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT</b>&#160;&#160;&#160;2</td></tr>
<tr class="separator:a27271abe3ee6cd79b56c0f7c478b7dbe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a904f5a2f2d12979b47f40661e769ddad"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a904f5a2f2d12979b47f40661e769ddad"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK</b>&#160;&#160;&#160;0x0F</td></tr>
<tr class="separator:a904f5a2f2d12979b47f40661e769ddad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a49bc9fc83d32004970e6d87829898b4d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a49bc9fc83d32004970e6d87829898b4d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK</b>&#160;&#160;&#160;0xF0</td></tr>
<tr class="separator:a49bc9fc83d32004970e6d87829898b4d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6faae2c2efedf10cb223a4b3da8cbe0f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6faae2c2efedf10cb223a4b3da8cbe0f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT</b>&#160;&#160;&#160;4</td></tr>
<tr class="separator:a6faae2c2efedf10cb223a4b3da8cbe0f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a18885b79b8fd7feae85721c4fef224d5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a18885b79b8fd7feae85721c4fef224d5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_SIGNAL_HPOLARITY_MASK</b>&#160;&#160;&#160;0x02</td></tr>
<tr class="separator:a18885b79b8fd7feae85721c4fef224d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa566229dcc4ffdc2baf1e8d6777789ce"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa566229dcc4ffdc2baf1e8d6777789ce"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_SIGNAL_VPOLARITY_MASK</b>&#160;&#160;&#160;0x04</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_SIGNAL_HPOLARITY_SHIFT</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_DTD_SIGNAL_VPOLARITY_SHIFT</b>&#160;&#160;&#160;2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_EDID_EXT_BLOCK_TAG_DISPID</b>&#160;&#160;&#160;0x70</td></tr>
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<tr class="memitem:a00702c4a2e9cd113a7c3898d8cbe64bc"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a00702c4a2e9cd113a7c3898d8cbe64bc"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_TAG</b>&#160;&#160;&#160;0x12</td></tr>
<tr class="separator:a00702c4a2e9cd113a7c3898d8cbe64bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a07ed3c6bc0d179a0b03aaecf279d8b1a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a07ed3c6bc0d179a0b03aaecf279d8b1a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_TOP0_HTOT_L_SHIFT</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_TOP0_HTOT_L_MASK</b>&#160;&#160;&#160;(0xF &lt;&lt; 4)</td></tr>
<tr class="separator:a0163da3a45ccb5a3fe15a2f53b305886"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac9d26ccc2bfaf74828dc65f8dd16f5bd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac9d26ccc2bfaf74828dc65f8dd16f5bd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_TOP0_VTOT_L_MASK</b>&#160;&#160;&#160;0xF</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_TOP1_HLOC_L_SHIFT</b>&#160;&#160;&#160;4</td></tr>
<tr class="separator:ad9b58e26ede14c0fb48db4185a564e31"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a65aa08a12157581d654a6469f368c6d0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a65aa08a12157581d654a6469f368c6d0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_TOP1_HLOC_L_MASK</b>&#160;&#160;&#160;(0xF &lt;&lt; 4)</td></tr>
<tr class="separator:a65aa08a12157581d654a6469f368c6d0"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_TOP1_VLOC_L_MASK</b>&#160;&#160;&#160;0xF</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_TOP2_HTOT_H_SHIFT</b>&#160;&#160;&#160;6</td></tr>
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<tr class="memitem:a65e86ed00f5769dd0b0ab5e32573a9d5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a65e86ed00f5769dd0b0ab5e32573a9d5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_TOP2_HTOT_H_MASK</b>&#160;&#160;&#160;(0x3 &lt;&lt; 6)</td></tr>
<tr class="separator:a65e86ed00f5769dd0b0ab5e32573a9d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5c98944db3b8b173ab3b23ae80625900"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5c98944db3b8b173ab3b23ae80625900"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_TOP2_VTOT_H_SHIFT</b>&#160;&#160;&#160;4</td></tr>
<tr class="separator:a5c98944db3b8b173ab3b23ae80625900"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a38c75939bf4cdb1e112cb6025ece77b3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a38c75939bf4cdb1e112cb6025ece77b3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_TOP2_VTOT_H_MASK</b>&#160;&#160;&#160;(0x3 &lt;&lt; 4)</td></tr>
<tr class="separator:a38c75939bf4cdb1e112cb6025ece77b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0add2b125e5419ec348217dd11bfe807"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0add2b125e5419ec348217dd11bfe807"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_TOP2_HLOC_H_SHIFT</b>&#160;&#160;&#160;2</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_TOP2_HLOC_H_MASK</b>&#160;&#160;&#160;(0x3 &lt;&lt; 2)</td></tr>
<tr class="separator:a34613258ad37a4ac81f560ce05955303"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPPSU_DISPID_TDT_TOP2_VLOC_H_MASK</b>&#160;&#160;&#160;0x3</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Register access macro definitions.</div></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDpPsu_In32</b>&#160;&#160;&#160;Xil_In32</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDpPsu_Out32</b>&#160;&#160;&#160;Xil_Out32</td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a2106632c315d3ad5f685330476ca417c"></a>
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          <td class="memname">#define XDPPSU_AUX_ADDRESS&#160;&#160;&#160;0x0108</td>
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<p>Specifies the address of current AUX command. </p>

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          <td class="memname">#define XDPPSU_AUX_CLK_DIVIDER&#160;&#160;&#160;0x010C</td>
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<p>Clock divider value for generating the internal 1MHz clock. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a2602de9c767cd981896326433a3c2570">XDpPsu_InitializeTx()</a>.</p>

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          <td class="memname">#define XDPPSU_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK&#160;&#160;&#160;0x0000FF00</td>
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<p>AUX (noise) signal width filter. </p>

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          <td class="memname">#define XDPPSU_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT&#160;&#160;&#160;8</td>
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<p>Shift bits for AUX signal width filter. </p>

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          <td class="memname">#define XDPPSU_AUX_CLK_DIVIDER_VAL_MASK&#160;&#160;&#160;0x000000FF</td>
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<p>Clock divider value. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a2602de9c767cd981896326433a3c2570">XDpPsu_InitializeTx()</a>.</p>

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</div>
<a class="anchor" id="a31902e97fbf794a6d9922965934a58e7"></a>
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          <td class="memname">#define XDPPSU_AUX_CMD&#160;&#160;&#160;0x0100</td>
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<p>Initiates AUX commands. </p>

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          <td class="memname">#define XDPPSU_AUX_CMD_ADDR_ONLY_TRANSFER_EN&#160;&#160;&#160;0x00001000</td>
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<p>Address only transfer enable (STOP will be sent after command). </p>

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          <td class="memname">#define XDPPSU_AUX_CMD_I2C_READ&#160;&#160;&#160;0x1</td>
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<p>I2C-over-AUX read command. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a17608072027dcae9a885b07ad2c25690">XDpPsu_IicRead()</a>.</p>

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          <td class="memname">#define XDPPSU_AUX_CMD_I2C_READ_MOT&#160;&#160;&#160;0x5</td>
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<p>I2C-over-AUX read MOT (middle-of-transaction) command. </p>

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          <td class="memname">#define XDPPSU_AUX_CMD_I2C_WRITE&#160;&#160;&#160;0x0</td>
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<p>I2C-over-AUX write command. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a22050229650e6ee5ac11242e5387e8e4">XDpPsu_IicWrite()</a>.</p>

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          <td class="memname">#define XDPPSU_AUX_CMD_I2C_WRITE_MOT&#160;&#160;&#160;0x4</td>
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<p>I2C-over-AUX write MOT (middle-of-transaction) command. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a17608072027dcae9a885b07ad2c25690">XDpPsu_IicRead()</a>.</p>

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</div>
<a class="anchor" id="afadde8f14c83776643cc1d40eb7a1c0c"></a>
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          <td class="memname">#define XDPPSU_AUX_CMD_I2C_WRITE_STATUS&#160;&#160;&#160;0x2</td>
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<p>I2C-over-AUX write status command. </p>

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          <td class="memname">#define XDPPSU_AUX_CMD_I2C_WRITE_STATUS_MOT&#160;&#160;&#160;0x6</td>
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<p>I2C-over-AUX write status MOT (middle-of- transaction) command. </p>

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          <td class="memname">#define XDPPSU_AUX_CMD_MASK&#160;&#160;&#160;0x00000F00</td>
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<p>AUX command. </p>

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          <td class="memname">#define XDPPSU_AUX_CMD_NBYTES_TRANSFER_MASK&#160;&#160;&#160;0x0000000F</td>
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<p>Number of bytes to transfer with the current AUX command. </p>

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          <td class="memname">#define XDPPSU_AUX_CMD_READ&#160;&#160;&#160;0x9</td>
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<p>AUX read command. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#ab9d129accbf09c6474ba5e1fac854983">XDpPsu_AuxRead()</a>.</p>

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          <td class="memname">#define XDPPSU_AUX_CMD_SHIFT&#160;&#160;&#160;8</td>
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<p>Shift bits for command. </p>

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          <td class="memname">#define XDPPSU_AUX_CMD_WRITE&#160;&#160;&#160;0x8</td>
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<p>AUX write command. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a619df5cbd94b7f0459e62b55a34e5df5">XDpPsu_AuxWrite()</a>.</p>

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          <td class="memname">#define XDPPSU_AUX_REPLY_CODE&#160;&#160;&#160;0x0138</td>
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<p>Reply code received from the most recent AUX command. </p>

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          <td class="memname">#define XDPPSU_AUX_REPLY_CODE_ACK&#160;&#160;&#160;0x0</td>
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<p>AUX command ACKed. </p>

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          <td class="memname">#define XDPPSU_AUX_REPLY_CODE_DEFER&#160;&#160;&#160;0x2</td>
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<p>AUX command deferred. </p>

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          <td class="memname">#define XDPPSU_AUX_REPLY_CODE_I2C_ACK&#160;&#160;&#160;0x0</td>
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<p>I2C-over-AUX command not ACKed. </p>

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<a class="anchor" id="a61a30cbd5c74f7c4e446cea776010d37"></a>
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          <td class="memname">#define XDPPSU_AUX_REPLY_CODE_I2C_DEFER&#160;&#160;&#160;0x8</td>
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<p>I2C-over-AUX command deferred. </p>

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          <td class="memname">#define XDPPSU_AUX_REPLY_CODE_I2C_NACK&#160;&#160;&#160;0x4</td>
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<p>I2C-over-AUX command not ACKed. </p>

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<a class="anchor" id="a5d1d3c855786c36190951ea9d8d97e63"></a>
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          <td class="memname">#define XDPPSU_AUX_REPLY_CODE_NACK&#160;&#160;&#160;0x1</td>
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<p>AUX command not ACKed. </p>

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<a class="anchor" id="a7721ad9f0a05d04280627008ea3fdaa0"></a>
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          <td class="memname">#define XDPPSU_AUX_REPLY_COUNT&#160;&#160;&#160;0x013C</td>
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<p>Number of reply transactions receieved over AUX. </p>

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          <td class="memname">#define XDPPSU_AUX_REPLY_DATA&#160;&#160;&#160;0x0134</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Reply data received during the AUX reply. </p>

</div>
</div>
<a class="anchor" id="a491175e394de4ec51f460abb147d7a1f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_AUX_WRITE_FIFO&#160;&#160;&#160;0x0104</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Write data for the current AUX command. </p>

</div>
</div>
<a class="anchor" id="ae89c4c9be38f83e506638165ea64cc19"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_COMP_PATTERN_80BIT_1&#160;&#160;&#160;0x0020</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bits [31:0] of the 80-bit custom pattern. </p>

</div>
</div>
<a class="anchor" id="aaf7e198c14d1dcdba81756020c94ceaf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_COMP_PATTERN_80BIT_2&#160;&#160;&#160;0x0024</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bits [63:32] of the 80-bit custom pattern. </p>

</div>
</div>
<a class="anchor" id="a427d39bb639fc7e4f1a7c4f04e712435"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_COMP_PATTERN_80BIT_3&#160;&#160;&#160;0x0028</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bits [79:64] of the 80-bit custom pattern. </p>

</div>
</div>
<a class="anchor" id="a838e534d7fa83c991d92ea2816e54e9b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_CORE_ID&#160;&#160;&#160;0x00FC</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DisplayPort revision. </p>

</div>
</div>
<a class="anchor" id="a3f23aee2514b6d668cda67d125a0c844"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_CORE_ID_DP_MJR_VER_MASK&#160;&#160;&#160;0x0000F000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DisplayPort protocol major version. </p>

</div>
</div>
<a class="anchor" id="a72f20d276edd42a8ba79582767527d9b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_CORE_ID_DP_MJR_VER_SHIFT&#160;&#160;&#160;24</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Shift bits for DisplayPort protocol major version. </p>

</div>
</div>
<a class="anchor" id="a5425dfe0c16d2930f19cdf73634d1e89"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_CORE_ID_DP_MNR_VER_MASK&#160;&#160;&#160;0x00000F00</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DisplayPort protocol minor version. </p>

</div>
</div>
<a class="anchor" id="a9aecb46049a8c94c958f6cdcb69e23f3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_CORE_ID_DP_MNR_VER_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Shift bits for DisplayPort protocol major version. </p>

</div>
</div>
<a class="anchor" id="ae73f897b46a59fdbaea6de897c93e924"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_CORE_ID_DP_REV_MASK&#160;&#160;&#160;0x000000F0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DisplayPort protocol revision. </p>

</div>
</div>
<a class="anchor" id="a4688b96899aa1f6a1b14fafe6f6fbe9a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_CORE_ID_DP_REV_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Shift bits for DisplayPort protocol revision. </p>

</div>
</div>
<a class="anchor" id="a1932581ae96af65a9525e241134a3afe"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_CORE_ID_TYPE_MASK&#160;&#160;&#160;0x0000000F</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Core type. </p>

</div>
</div>
<a class="anchor" id="a0a7400909e42e7f017683666bb8a08a6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_CORE_ID_TYPE_RX&#160;&#160;&#160;0x1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Core is a receiver. </p>

</div>
</div>
<a class="anchor" id="af51a9b5493acbb0f6275fb71ed88f052"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_CORE_ID_TYPE_TX&#160;&#160;&#160;0x0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Core is a transmitter. </p>

</div>
</div>
<a class="anchor" id="ad4beaa963b7a63da99c8663caa7c7440"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_DOWNSPREAD_CTRL&#160;&#160;&#160;0x0018</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Enable a 0.5% spreading of the clock. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a7836168f290562156a24fb51762acde4">XDpPsu_SetDownspread()</a>.</p>

</div>
</div>
<a class="anchor" id="a96dd8a3fe382bc8e7ae78429c44b7d52"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_DP_DISABLE&#160;&#160;&#160;0x0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This field disables the DisplayPort core. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a2602de9c767cd981896326433a3c2570">XDpPsu_InitializeTx()</a>.</p>

</div>
</div>
<a class="anchor" id="ab18f03371514f98187b96e9350c03816"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_DP_ENABLE&#160;&#160;&#160;0x1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This field enables the DisplayPort core. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a2602de9c767cd981896326433a3c2570">XDpPsu_InitializeTx()</a>.</p>

</div>
</div>
<a class="anchor" id="a18e71ddca3a5336d64bdf3a7ed75e3f9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_ENABLE&#160;&#160;&#160;0x0080</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Enable the basic operations of the DisplayPort TX core or output stuffing symbols if disabled. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a2602de9c767cd981896326433a3c2570">XDpPsu_InitializeTx()</a>, and <a class="el" href="xdppsu_8h.html#a6eec1f08aa677fac3467a9d34b54589c">XDpPsu_ResetPhy()</a>.</p>

</div>
</div>
<a class="anchor" id="a13298309408d465cf884b2b5eb78009b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_ENABLE_MAIN_STREAM&#160;&#160;&#160;0x0084</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Enable transmission of main link video info. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#ad113ed848850849d07fae7ce163a8a62">XDpPsu_EnableMainLink()</a>, and <a class="el" href="xdppsu_8h.html#abe31bd9b101b094a40eff13ef032ea44">XDpPsu_EstablishLink()</a>.</p>

</div>
</div>
<a class="anchor" id="acb217703567249190f6250fba75a0a38"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_ENHANCED_FRAME_EN&#160;&#160;&#160;0x0008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Enable enhanced framing symbol sequence. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a2ec5ae4af1f5232fc86116d457045997">XDpPsu_SetEnhancedFrameMode()</a>.</p>

</div>
</div>
<a class="anchor" id="aa04733c4a40ad233e107c38c163a3423"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_FORCE_SCRAMBLER_RESET&#160;&#160;&#160;0x00C0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Force a scrambler reset. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#ad113ed848850849d07fae7ce163a8a62">XDpPsu_EnableMainLink()</a>.</p>

</div>
</div>
<a class="anchor" id="a2221a5ada815d383adda40c0badcb74d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_FRAC_BYTES_PER_TU&#160;&#160;&#160;0x01C8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>The fractional component when calculated the XDPPSU_MIN_BYTES_PER_TU register value. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>.</p>

</div>
</div>
<a class="anchor" id="a728bb80efc84e6cb161e3f04103bf6ed"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_HPD_DURATION&#160;&#160;&#160;0x0150</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Duration of the HPD pulse in microseconds. </p>

<p>Referenced by <a class="el" href="xdppsu__intr_8c.html#a940393f7b33c36e51ea69d4561630222">XDpPsu_HpdInterruptHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ac1bfc95808e680c14095348df796eff3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INIT_WAIT&#160;&#160;&#160;0x01CC</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Number of initial wait cycles at the start of a new line by the framing logic, allowing enough data to be buffered in the input FIFO. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>.</p>

</div>
</div>
<a class="anchor" id="a3f100eb641ca948e3ae71bb33b5e6512"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTERRUPT_SIG_STATE&#160;&#160;&#160;0x0130</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>The raw signal values for interupt events. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#aee45a79c993e3bcad636dddf3121aeab">XDpPsu_IsConnected()</a>.</p>

</div>
</div>
<a class="anchor" id="abe45f09e082e6ceecb66597575dac0e7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTERRUPT_SIG_STATE_HPD_STATE_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Raw state of the HPD pin on the DP connector. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#aee45a79c993e3bcad636dddf3121aeab">XDpPsu_IsConnected()</a>.</p>

</div>
</div>
<a class="anchor" id="af6414260592c508ef5410355a8940834"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTERRUPT_SIG_STATE_REPLY_STATE_MASK&#160;&#160;&#160;0x00000004</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>A reply is currently being received. </p>

</div>
</div>
<a class="anchor" id="a08ade06a64e915ca736c49fb5e6836ef"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTERRUPT_SIG_STATE_REPLY_TIMEOUT_MASK&#160;&#160;&#160;0x00000008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>A reply timeout has occurred. </p>

</div>
</div>
<a class="anchor" id="a4d3e7112cc860981d1becb976cc6e2a1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTERRUPT_SIG_STATE_REQUEST_STATE_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>A request is currently being sent. </p>

</div>
</div>
<a class="anchor" id="ad5113d356b9c8fd6267e021b75edd364"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTR_CHBUF0_OVERFLW_MASK&#160;&#160;&#160;0x08000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AV buffer manager channel buffer 0 overflow. </p>

</div>
</div>
<a class="anchor" id="adb8065c93945e4783ae56e08b3832a5b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTR_CHBUF0_UNDERFLW_MASK&#160;&#160;&#160;0x00200000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AV buffer manager channel buffer 0 underflow. </p>

</div>
</div>
<a class="anchor" id="a8db1b3424e328e29cacea2334574dcb1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTR_CHBUF1_OVERFLW_MASK&#160;&#160;&#160;0x04000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AV buffer manager channel buffer 1 overflow. </p>

</div>
</div>
<a class="anchor" id="a29ec84c65e201cc8549a1b6c62959831"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTR_CHBUF1_UNDERFLW_MASK&#160;&#160;&#160;0x00100000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AV buffer manager channel buffer 1 underflow. </p>

</div>
</div>
<a class="anchor" id="a39a9592b65b1635198bbde9e4adcab37"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTR_CHBUF2_OVERFLW_MASK&#160;&#160;&#160;0x02000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AV buffer manager channel buffer 2 overflow. </p>

</div>
</div>
<a class="anchor" id="ad391bfc383276a337b92ee23c11677ad"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTR_CHBUF2_UNDERFLW_MASK&#160;&#160;&#160;0x00080000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AV buffer manager channel buffer 2 underflow. </p>

</div>
</div>
<a class="anchor" id="a7571f776db070b66f2f2a86308db39f0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTR_CHBUF3_OVERFLW_MASK&#160;&#160;&#160;0x01000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AV buffer manager channel buffer 3 overflow. </p>

</div>
</div>
<a class="anchor" id="a2cc02e429a27f26b8b5db19aeeabfdaf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTR_CHBUF3_UNDERFLW_MASK&#160;&#160;&#160;0x00040000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AV buffer manager channel buffer 3 underflow. </p>

</div>
</div>
<a class="anchor" id="a0d3f4391a441d40cef2419d2c0795dad"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTR_CHBUF4_OVERFLW_MASK&#160;&#160;&#160;0x00800000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AV buffer manager channel buffer 4 overflow. </p>

</div>
</div>
<a class="anchor" id="a10c8cc1cb4610a2165ee38673b247d1b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTR_CHBUF4_UNDERFLW_MASK&#160;&#160;&#160;0x00020000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AV buffer manager channel buffer 4 underflow. </p>

</div>
</div>
<a class="anchor" id="ac1d170e10ff34c6cac0a5a178f661776"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTR_CHBUF5_OVERFLW_MASK&#160;&#160;&#160;0x00400000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AV buffer manager channel buffer 5 overflow. </p>

</div>
</div>
<a class="anchor" id="a1d8c73cf290587e5915d0c4e6049cb0a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTR_CHBUF5_UNDERFLW_MASK&#160;&#160;&#160;0x00010000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AV buffer manager channel buffer 5 underflow. </p>

</div>
</div>
<a class="anchor" id="a587a6015742d74938f7fe657fee359b6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTR_CUST_TS_2_MASK&#160;&#160;&#160;0x10000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Indicates that a user defined custom event 2 has triggered a timestamp. </p>

</div>
</div>
<a class="anchor" id="abebc492322f633e84cdff5b1843759bb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTR_CUST_TS_MASK&#160;&#160;&#160;0x20000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Indicates that a user defined custom event has triggered a timestamp. </p>

</div>
</div>
<a class="anchor" id="aed1c38a089b2e11a4e182a0d7d3d7581"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTR_DIS&#160;&#160;&#160;0x03AC</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt disable register. </p>

</div>
</div>
<a class="anchor" id="a4df905812adc82df8d8c84ade4093acf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTR_EN&#160;&#160;&#160;0x03A8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt enable register. </p>

</div>
</div>
<a class="anchor" id="aca97dd11e3816f52fea1b6d1ef6ab182"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_INTR_EXT_PKT_TXD_MASK&#160;&#160;&#160;0x00000020</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Extended packet has been transmitted and the core is ready to accept a new packet. </p>

</div>
</div>
<a class="anchor" id="a258f7a242c29b8fb48a375501f9c6a38"></a>
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          <td class="memname">#define XDPPSU_INTR_EXT_VSYNC_TS_MASK&#160;&#160;&#160;0x40000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Indicates that an external VSYNC has triggered a timestamp. </p>
<p>This is generated on every posedge of the external VSYNC signal. </p>

</div>
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<a class="anchor" id="a3c97c07d18d9c5a39382fb8f8f7518b6"></a>
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          <td class="memname">#define XDPPSU_INTR_HPD_EVENT_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
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<p>Detected the presence of the HPD signal. </p>

<p>Referenced by <a class="el" href="xdppsu__intr_8c.html#a940393f7b33c36e51ea69d4561630222">XDpPsu_HpdInterruptHandler()</a>, <a class="el" href="xdppsu_8h.html#a17608072027dcae9a885b07ad2c25690">XDpPsu_IicRead()</a>, and <a class="el" href="xdppsu_8h.html#a2602de9c767cd981896326433a3c2570">XDpPsu_InitializeTx()</a>.</p>

</div>
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          <td class="memname">#define XDPPSU_INTR_HPD_IRQ_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Detected an IRQ framed with the proper timing on the HPD signal. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a2602de9c767cd981896326433a3c2570">XDpPsu_InitializeTx()</a>.</p>

</div>
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<a class="anchor" id="a63c73ef7b94ee2b16928d5423226e636"></a>
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          <td class="memname">#define XDPPSU_INTR_HPD_PULSE_DETECTED_MASK&#160;&#160;&#160;0x00000010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>A pulse on the HPD line was detected. </p>

<p>Referenced by <a class="el" href="xdppsu__intr_8c.html#a940393f7b33c36e51ea69d4561630222">XDpPsu_HpdInterruptHandler()</a>, and <a class="el" href="xdppsu_8h.html#a2602de9c767cd981896326433a3c2570">XDpPsu_InitializeTx()</a>.</p>

</div>
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<a class="anchor" id="a3f1b69b1c773f27b9177eccedefc70ce"></a>
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          <td class="memname">#define XDPPSU_INTR_LIV_ABUF_UNDRFLW_MASK&#160;&#160;&#160;0x00001000</td>
        </tr>
      </table>
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<p>Interrupt asserted when live audio is enabled at subsystem, but the input does not match audio sample rate. </p>

</div>
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<a class="anchor" id="a7961eb41e1c88de739f7462d44818b4c"></a>
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<div class="memproto">
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          <td class="memname">#define XDPPSU_INTR_MASK&#160;&#160;&#160;0x03A4</td>
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      </table>
</div><div class="memdoc">

<p>Masks the specified interrupt sources. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a2602de9c767cd981896326433a3c2570">XDpPsu_InitializeTx()</a>.</p>

</div>
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<a class="anchor" id="ac3e3297900544ef6e07f2f4327a92f92"></a>
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<div class="memproto">
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          <td class="memname">#define XDPPSU_INTR_PIXEL0_MATCH_MASK&#160;&#160;&#160;0x00008000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>When VCOUNT and HCOUNT from AV buffer manager register 0x074 matches early VCOUNT. </p>

</div>
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<a class="anchor" id="a3bb90175ec9b586e94ec756c6ea1f4d6"></a>
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<div class="memproto">
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          <td class="memname">#define XDPPSU_INTR_PIXEL1_MATCH_MASK&#160;&#160;&#160;0x00004000</td>
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</div><div class="memdoc">

<p>When VCOUNT and HCOUNT from AV buffer manager register 0x078 matches early VCOUNT. </p>

</div>
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<a class="anchor" id="a541b41f7d1c9b568d4329ba9407851d0"></a>
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          <td class="memname">#define XDPPSU_INTR_REPLY_RECEIVED_MASK&#160;&#160;&#160;0x00000004</td>
        </tr>
      </table>
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<p>An AUX reply transaction has been detected. </p>

</div>
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<a class="anchor" id="a294c84ec5b18a80d4179d9e1b297bba5"></a>
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<div class="memproto">
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          <td class="memname">#define XDPPSU_INTR_REPLY_TIMEOUT_MASK&#160;&#160;&#160;0x00000008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>A reply timeout has occurred. </p>

</div>
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<a class="anchor" id="a66cf1bc6e98aa546ba11f8a8091b1f8e"></a>
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<div class="memproto">
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          <td class="memname">#define XDPPSU_INTR_STATUS&#160;&#160;&#160;0x03A0</td>
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      </table>
</div><div class="memdoc">

<p>Status for interrupt events. </p>

<p>Referenced by <a class="el" href="xdppsu__intr_8c.html#a940393f7b33c36e51ea69d4561630222">XDpPsu_HpdInterruptHandler()</a>, and <a class="el" href="xdppsu_8h.html#a17608072027dcae9a885b07ad2c25690">XDpPsu_IicRead()</a>.</p>

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<a class="anchor" id="a8818806e37ca6066c15b8c69360ae630"></a>
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<div class="memproto">
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          <td class="memname">#define XDPPSU_INTR_VBLNK_START_MASK&#160;&#160;&#160;0x00002000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt at start of early vertical blanking. </p>

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<a class="anchor" id="ae000f500b8922ed564f17d073967bfe9"></a>
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<div class="memproto">
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          <td class="memname">#define XDPPSU_INTR_VSYNC_TS_MASK&#160;&#160;&#160;0x80000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Indicates that a VSYNC timestamp is available. </p>
<p>This is generated on every VSYNC event. </p>

</div>
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<a class="anchor" id="a25090ba43a6682938a143310ed73d844"></a>
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          <td class="memname">#define XDPPSU_LANE_COUNT_SET&#160;&#160;&#160;0x0004</td>
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      </table>
</div><div class="memdoc">

<p>Set lane count setting. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a868ca9bd2184707f3929e6f7e695cc93">XDpPsu_SetLaneCount()</a>.</p>

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<a class="anchor" id="ab2400bfc1fa2146da8072bbd146f4389"></a>
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<div class="memproto">
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          <td class="memname">#define XDPPSU_LANE_COUNT_SET_1&#160;&#160;&#160;0x01</td>
        </tr>
      </table>
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<p>Lane count of 1. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a60932e88ba047ac16f0b6ce9103d43b7">XDpPsu_CfgMsaRecalculate()</a>, <a class="el" href="xdppsu_8h.html#ae723bbc24a4dbce124cdd92979af27af">XDpPsu_CheckLinkStatus()</a>, and <a class="el" href="xdppsu_8h.html#abe31bd9b101b094a40eff13ef032ea44">XDpPsu_EstablishLink()</a>.</p>

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<a class="anchor" id="a07e8772a5d5bc27127f948b47122cec4"></a>
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<div class="memproto">
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          <td class="memname">#define XDPPSU_LANE_COUNT_SET_2&#160;&#160;&#160;0x02</td>
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      </table>
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<p>Lane count of 2. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a60932e88ba047ac16f0b6ce9103d43b7">XDpPsu_CfgMsaRecalculate()</a>, <a class="el" href="xdppsu_8h.html#ae723bbc24a4dbce124cdd92979af27af">XDpPsu_CheckLinkStatus()</a>, and <a class="el" href="xdppsu_8h.html#abe31bd9b101b094a40eff13ef032ea44">XDpPsu_EstablishLink()</a>.</p>

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<a class="anchor" id="a39533d8f8e18fce7b13f84d440b6b176"></a>
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          <td class="memname">#define XDPPSU_LINK_BW_SET&#160;&#160;&#160;0x0000</td>
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      </table>
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<p>Set main link bandwidth setting. </p>

<p>Referenced by <a class="el" href="xdppsu__common__example_8h.html#a64d2267afa217a44aa3bf09bcd51e409">DpPsu_StartLink()</a>, and <a class="el" href="xdppsu_8h.html#a68384c6a808dff1f2e68e7611057a548">XDpPsu_SetLinkRate()</a>.</p>

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<a class="anchor" id="af641cdc72bb85675494a1c463904f8e1"></a>
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<div class="memproto">
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          <td class="memname">#define XDPPSU_LINK_BW_SET_162GBPS&#160;&#160;&#160;0x06</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>1.62 Gbps link rate. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a60932e88ba047ac16f0b6ce9103d43b7">XDpPsu_CfgMsaRecalculate()</a>, <a class="el" href="xdppsu_8h.html#abe31bd9b101b094a40eff13ef032ea44">XDpPsu_EstablishLink()</a>, and <a class="el" href="xdppsu_8h.html#a68384c6a808dff1f2e68e7611057a548">XDpPsu_SetLinkRate()</a>.</p>

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<a class="anchor" id="a826616f141ab667c2f91c83507ce2322"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XDPPSU_LINK_BW_SET_270GBPS&#160;&#160;&#160;0x0A</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>2.70 Gbps link rate. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a60932e88ba047ac16f0b6ce9103d43b7">XDpPsu_CfgMsaRecalculate()</a>, <a class="el" href="xdppsu_8h.html#abe31bd9b101b094a40eff13ef032ea44">XDpPsu_EstablishLink()</a>, and <a class="el" href="xdppsu_8h.html#a68384c6a808dff1f2e68e7611057a548">XDpPsu_SetLinkRate()</a>.</p>

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<a class="anchor" id="ab01ff3802386be5d138cf5a9af031783"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XDPPSU_LINK_BW_SET_540GBPS&#160;&#160;&#160;0x14</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>5.40 Gbps link rate. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a60932e88ba047ac16f0b6ce9103d43b7">XDpPsu_CfgMsaRecalculate()</a>, <a class="el" href="xdppsu_8h.html#abe31bd9b101b094a40eff13ef032ea44">XDpPsu_EstablishLink()</a>, and <a class="el" href="xdppsu_8h.html#a68384c6a808dff1f2e68e7611057a548">XDpPsu_SetLinkRate()</a>.</p>

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</div>
<a class="anchor" id="a637f77a0a0d58a0c55799c07ceb8fa62"></a>
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<div class="memproto">
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          <td class="memname">#define XDPPSU_LINK_QUAL_PATTERN_SET&#160;&#160;&#160;0x0010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Transmit the link quality pattern. </p>

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<a class="anchor" id="adc73b05c94da6e1c36d0bebbc8957488"></a>
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          <td class="memname">#define XDPPSU_LINK_QUAL_PATTERN_SET_80B_CUSTOM&#160;&#160;&#160;0x4</td>
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      </table>
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<p>80-bit custom pattern. </p>

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<a class="anchor" id="a3bd3f2849a7d89187c1dd623dea3c24d"></a>
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<div class="memproto">
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          <td class="memname">#define XDPPSU_LINK_QUAL_PATTERN_SET_D102_TEST&#160;&#160;&#160;0x1</td>
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      </table>
</div><div class="memdoc">

<p>D10.2 unscrambled test pattern transmitted. </p>

</div>
</div>
<a class="anchor" id="a932ba29315d349fc2d37fcbf92d884d2"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XDPPSU_LINK_QUAL_PATTERN_SET_EXT_MASK&#160;&#160;&#160;0x4</td>
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      </table>
</div><div class="memdoc">

<p>Used for HBR2 compliance and 80-bit custom patterns. </p>

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<a class="anchor" id="a231835618553eadbf8738d9992de34ed"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XDPPSU_LINK_QUAL_PATTERN_SET_HBR2_COMP&#160;&#160;&#160;0x5</td>
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      </table>
</div><div class="memdoc">

<p>HBR2 compliance pattern. </p>

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<a class="anchor" id="ac594adc36322663f5281ce39a5bedf91"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XDPPSU_LINK_QUAL_PATTERN_SET_OFF&#160;&#160;&#160;0x0</td>
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<p>Link quality test pattern not transmitted. </p>

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<a class="anchor" id="a152631a04673c1ba60de6b167f200ff0"></a>
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<div class="memproto">
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          <td class="memname">#define XDPPSU_LINK_QUAL_PATTERN_SET_PRBS7&#160;&#160;&#160;0x3</td>
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</div><div class="memdoc">

<p>Pseudo random bit sequence 7 transmitted. </p>

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<a class="anchor" id="ae5b3264185b7d7eb74026d8c9cba83fc"></a>
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<div class="memproto">
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          <td class="memname">#define XDPPSU_LINK_QUAL_PATTERN_SET_SER_MES&#160;&#160;&#160;0x2</td>
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      </table>
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<p>Symbol error rate measurement pattern transmitted. </p>

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<a class="anchor" id="ae42d697245eb12b0caae5f2cdec459ed"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XDPPSU_M_VID&#160;&#160;&#160;0x01AC</td>
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<p>M value for the video stream as computed by the source core in asynchronous clock mode. </p>
<p>Must be written in synchronous mode. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>.</p>

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<a class="anchor" id="a27ba254de82f62941d184b8962dca6a9"></a>
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<div class="memproto">
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          <td class="memname">#define XDPPSU_MAIN_STREAM_HRES&#160;&#160;&#160;0x0194</td>
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<p>Number of active pixels per line (the horizontal resolution). </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>.</p>

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<a class="anchor" id="a6515d0120b4a6fcd2769d651f9c85335"></a>
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<div class="memproto">
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          <td class="memname">#define XDPPSU_MAIN_STREAM_HSTART&#160;&#160;&#160;0x019C</td>
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<p>Number of clocks between the leading edge of the horizontal sync and the start of active data. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>.</p>

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<a class="anchor" id="a12ef125fc3c17f329374fb7082d91e81"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XDPPSU_MAIN_STREAM_HSWIDTH&#160;&#160;&#160;0x018C</td>
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<p>Width of the horizontal sync pulse. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>.</p>

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<a class="anchor" id="acfae349a9726fe324642e099ebbfb356"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_HTOTAL&#160;&#160;&#160;0x0180</td>
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<p>Total number of clocks in the horizontal framing period. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>.</p>

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</div>
<a class="anchor" id="a4c8b7aedd1df781e3ca81a9d54fd3e6a"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0&#160;&#160;&#160;0x01A4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Miscellaneous stream attributes. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>.</p>

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</div>
<a class="anchor" id="a543471a6b6f68ec7fa64c4bdc159aef6"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_BDC_10BPC&#160;&#160;&#160;0x2</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>10 bits per component. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a60932e88ba047ac16f0b6ce9103d43b7">XDpPsu_CfgMsaRecalculate()</a>.</p>

</div>
</div>
<a class="anchor" id="a0f4025e10b15002c31e67ff319167574"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_BDC_12BPC&#160;&#160;&#160;0x3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>12 bits per component. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a60932e88ba047ac16f0b6ce9103d43b7">XDpPsu_CfgMsaRecalculate()</a>.</p>

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</div>
<a class="anchor" id="adc5bca138020f36f2ff54990a53f3bc4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_BDC_16BPC&#160;&#160;&#160;0x4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>16 bits per component. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a60932e88ba047ac16f0b6ce9103d43b7">XDpPsu_CfgMsaRecalculate()</a>.</p>

</div>
</div>
<a class="anchor" id="a28c8927d5dbc09c1767415b65b68ee57"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_BDC_6BPC&#160;&#160;&#160;0x0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>6 bits per component. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a60932e88ba047ac16f0b6ce9103d43b7">XDpPsu_CfgMsaRecalculate()</a>.</p>

</div>
</div>
<a class="anchor" id="a4c4cf8ebf3908d41f086aa164047dc88"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_BDC_8BPC&#160;&#160;&#160;0x1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>8 bits per component. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a60932e88ba047ac16f0b6ce9103d43b7">XDpPsu_CfgMsaRecalculate()</a>.</p>

</div>
</div>
<a class="anchor" id="a9d547e518f891c4b31590ba71cb6ed75"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_BDC_MASK&#160;&#160;&#160;0x000000E0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit depth per color component (BDC). </p>

</div>
</div>
<a class="anchor" id="acee2c3a2e5360398cf20d669767f0838"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_BDC_SHIFT&#160;&#160;&#160;5</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Shift bits for BDC. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a60932e88ba047ac16f0b6ce9103d43b7">XDpPsu_CfgMsaRecalculate()</a>.</p>

</div>
</div>
<a class="anchor" id="a75ce663ac0c55c70e31f29771291bd5e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_COMPONENT_FORMAT_MASK&#160;&#160;&#160;0x00000006</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Component format. </p>

</div>
</div>
<a class="anchor" id="a62cef3c8f37c23bbcb361cf27e78b79a"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_COMPONENT_FORMAT_RGB&#160;&#160;&#160;0x0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Stream's component format is RGB. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a93872e0beb0405b47b7d689e8f8749c5">XDpPsu_SetColorEncode()</a>.</p>

</div>
</div>
<a class="anchor" id="a2db3e057d0bf4c18c078c8c6c1c6e214"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_COMPONENT_FORMAT_SHIFT&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Shift bits for component format. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a288a08c1d83e4f66f0217cab4d695544">XDpPsu_CfgMsaEnSynchClkMode()</a>, and <a class="el" href="xdppsu__spm_8c.html#a60932e88ba047ac16f0b6ce9103d43b7">XDpPsu_CfgMsaRecalculate()</a>.</p>

</div>
</div>
<a class="anchor" id="aa7f01b729a14459dd1dd702396841e67"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_COMPONENT_FORMAT_YCBCR422&#160;&#160;&#160;0x1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Stream's component format is YcbCr 4:2:2. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a60932e88ba047ac16f0b6ce9103d43b7">XDpPsu_CfgMsaRecalculate()</a>, and <a class="el" href="xdppsu__spm_8c.html#a93872e0beb0405b47b7d689e8f8749c5">XDpPsu_SetColorEncode()</a>.</p>

</div>
</div>
<a class="anchor" id="acf4d40b05aab671f8d7339ce3b3a1bff"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_COMPONENT_FORMAT_YCBCR444&#160;&#160;&#160;0x2</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Stream's component format is YcbCr 4:4:4. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a93872e0beb0405b47b7d689e8f8749c5">XDpPsu_SetColorEncode()</a>.</p>

</div>
</div>
<a class="anchor" id="a7584fd929b074b9678cc208f150084c7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_DYNAMIC_RANGE_CEA&#160;&#160;&#160;0x00000008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>CEA range. </p>

</div>
</div>
<a class="anchor" id="aac1319fb0218b78cd03a735255f973f5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_DYNAMIC_RANGE_MASK&#160;&#160;&#160;0x00000008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Dynamic range. </p>

</div>
</div>
<a class="anchor" id="a848bedf3fe17154e8b43d5dc9001021d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_DYNAMIC_RANGE_SHIFT&#160;&#160;&#160;3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Shift bits for dynamic range. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a60932e88ba047ac16f0b6ce9103d43b7">XDpPsu_CfgMsaRecalculate()</a>.</p>

</div>
</div>
<a class="anchor" id="a9b99ddae9071dc99417a6e82d5e124c3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_DYNAMIC_RANGE_VESA&#160;&#160;&#160;0x00000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VESA range. </p>

</div>
</div>
<a class="anchor" id="a91cf45127ce9176bb5daf96f07c8cddc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_SYNC_CLK_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Synchronous clock. </p>

</div>
</div>
<a class="anchor" id="aeea7a0870811c648c1f14c54b7eea604"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_YCBCR_COLORIMETRY_ITU_BT601&#160;&#160;&#160;0x00000010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>ITU601 YCbCr coefficients. </p>

</div>
</div>
<a class="anchor" id="ac1311bc1fa0ca578e1c5ef5b03830aec"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_YCBCR_COLORIMETRY_ITU_BT709&#160;&#160;&#160;0x00000010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>ITU709 YCbCr coefficients. </p>

</div>
</div>
<a class="anchor" id="a191ea628e4913d1a8d44043a64935f1b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_YCBCR_COLORIMETRY_MASK&#160;&#160;&#160;0x00000010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>YCbCr colorimetry. </p>

</div>
</div>
<a class="anchor" id="a758fdab5131d4991458d3a515d4304ac"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC0_YCBCR_COLORIMETRY_SHIFT&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Shift bits for YCbCr colorimetry. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a60932e88ba047ac16f0b6ce9103d43b7">XDpPsu_CfgMsaRecalculate()</a>.</p>

</div>
</div>
<a class="anchor" id="a68bdadc636b21a7130f9d6f2444b6908"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC1&#160;&#160;&#160;0x01A8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Miscellaneous stream attributes. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>.</p>

</div>
</div>
<a class="anchor" id="ab55517d8d6c777fd0d50c2b6ec04c559"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC1_STEREO_VID_ATTR_MASK&#160;&#160;&#160;0x00000006</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Stereo video attribute. </p>

</div>
</div>
<a class="anchor" id="a64e74ed760224ac4dcfad41ac58dd34f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC1_STEREO_VID_ATTR_SHIFT&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Shift bits for stereo video attribute. </p>

</div>
</div>
<a class="anchor" id="a3a788946c8a8f00681b5a2493af74667"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_MISC1_Y_ONLY_EN_MASK&#160;&#160;&#160;0x00000080</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Y only enable. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a60932e88ba047ac16f0b6ce9103d43b7">XDpPsu_CfgMsaRecalculate()</a>, and <a class="el" href="xdppsu__spm_8c.html#a93872e0beb0405b47b7d689e8f8749c5">XDpPsu_SetColorEncode()</a>.</p>

</div>
</div>
<a class="anchor" id="aa7738c02d0883e7d17f1ab000af800de"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_POLARITY&#160;&#160;&#160;0x0188</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Polarity for the video sync signals. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>.</p>

</div>
</div>
<a class="anchor" id="adf93e2b972e6ad2a0217efff40d0c605"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_POLARITY_HSYNC_POL_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Polarity of the horizontal sync pulse. </p>

</div>
</div>
<a class="anchor" id="a6165afdbbd6e43863b5dec77fbff7255"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_POLARITY_VSYNC_POL_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Polarity of the vertical sync pulse. </p>

</div>
</div>
<a class="anchor" id="ae227c02effff3397f8a882aaf587b436"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_POLARITY_VSYNC_POL_SHIFT&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Shift bits for polarity of the vertical sync pulse. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>.</p>

</div>
</div>
<a class="anchor" id="a9d8763c359f1036ef3af7aabd92fc61b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_VRES&#160;&#160;&#160;0x0198</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Number of active lines (the vertical resolution). </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>.</p>

</div>
</div>
<a class="anchor" id="adaccb873812cdd56a0a9400f525bccb0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_VSTART&#160;&#160;&#160;0x01A0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Number of lines between the leading edge of the vertical sync and the first line of active data. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>.</p>

</div>
</div>
<a class="anchor" id="a89b4198d0838f5b13c3efc018bfff63e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_VSWIDTH&#160;&#160;&#160;0x0190</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Width of the vertical sync pulse. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>.</p>

</div>
</div>
<a class="anchor" id="aa4d7607e0a3dbca00150115881ecca65"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MAIN_STREAM_VTOTAL&#160;&#160;&#160;0x0184</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Total number of lines in the video frame. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>.</p>

</div>
</div>
<a class="anchor" id="ae809ab48c87900a9b2cd219d8385f3d5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_MIN_BYTES_PER_TU&#160;&#160;&#160;0x01C4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>The minimum number of bytes per transfer unit. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>.</p>

</div>
</div>
<a class="anchor" id="a402b43e835fbfff366b961880262d3ba"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_N_VID&#160;&#160;&#160;0x01B4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>N value for the video stream as computed by the source core in asynchronous clock mode. </p>
<p>Must be written in synchronous mode. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>.</p>

</div>
</div>
<a class="anchor" id="a35f964035ad6eade3df5b8539989b536"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_PHY_CLOCK_SELECT&#160;&#160;&#160;0x0234</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Instructs the PHY PLL to generate the proper clock frequency for the required link rate. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a2602de9c767cd981896326433a3c2570">XDpPsu_InitializeTx()</a>.</p>

</div>
</div>
<a class="anchor" id="a89ac9477adf2f20000d1b6f9d4adb617"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_PHY_CLOCK_SELECT_162GBPS&#160;&#160;&#160;0x1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>1.62 Gbps link. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a68384c6a808dff1f2e68e7611057a548">XDpPsu_SetLinkRate()</a>.</p>

</div>
</div>
<a class="anchor" id="ad41a2cbf2a3730426b20ab8b1cd7f257"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_PHY_CLOCK_SELECT_270GBPS&#160;&#160;&#160;0x3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>2.70 Gbps link. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a68384c6a808dff1f2e68e7611057a548">XDpPsu_SetLinkRate()</a>.</p>

</div>
</div>
<a class="anchor" id="ac235ac35ed4fb7136ed096c754ad0c2f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_PHY_CLOCK_SELECT_540GBPS&#160;&#160;&#160;0x5</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>5.40 Gbps link. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a2602de9c767cd981896326433a3c2570">XDpPsu_InitializeTx()</a>, and <a class="el" href="xdppsu_8h.html#a68384c6a808dff1f2e68e7611057a548">XDpPsu_SetLinkRate()</a>.</p>

</div>
</div>
<a class="anchor" id="ad564b6d94b00f66d20f2469f924a0a19"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_PHY_CONFIG&#160;&#160;&#160;0x0200</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Transceiver PHY reset and configuration. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a2602de9c767cd981896326433a3c2570">XDpPsu_InitializeTx()</a>, and <a class="el" href="xdppsu_8h.html#a6eec1f08aa677fac3467a9d34b54589c">XDpPsu_ResetPhy()</a>.</p>

</div>
</div>
<a class="anchor" id="a28a9751ea84fe5ab784defeb1f5b203b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_PHY_CONFIG_GT_ALL_RESET_MASK&#160;&#160;&#160;0x0000003</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Reset GT and PHY. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a2602de9c767cd981896326433a3c2570">XDpPsu_InitializeTx()</a>.</p>

</div>
</div>
<a class="anchor" id="a65c40b0e93ec7b7f50cfec29c6f1a1e1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_PHY_CONFIG_GTTX_RESET_MASK&#160;&#160;&#160;0x0000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Hold GTTXRESET in reset. </p>

</div>
</div>
<a class="anchor" id="a14b7b68d4e2f30ef852e03eeb0743929"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XDPPSU_PHY_CONFIG_PHY_RESET_ENABLE_MASK&#160;&#160;&#160;0x0000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Release reset. </p>

</div>
</div>
<a class="anchor" id="a848fe33e971d0e24ed48e966024dfb9a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_PHY_CONFIG_PHY_RESET_MASK&#160;&#160;&#160;0x0000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Hold the PHY in reset. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#abe31bd9b101b094a40eff13ef032ea44">XDpPsu_EstablishLink()</a>.</p>

</div>
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<a class="anchor" id="aba0f41405e22038988f7198add44b5cc"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XDPPSU_PHY_CONFIG_TX_PHY_8B10BEN_MASK&#160;&#160;&#160;0x0010000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>8B10B encoding enable. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#abe31bd9b101b094a40eff13ef032ea44">XDpPsu_EstablishLink()</a>.</p>

</div>
</div>
<a class="anchor" id="afd27646d6bf849e2605ec977e0906bb0"></a>
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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_PHY_PRECURSOR_LANE_0&#160;&#160;&#160;0x024C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Controls the pre-cursor level. </p>

</div>
</div>
<a class="anchor" id="a6b8dfc6e98b73a331306b25535d484bb"></a>
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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_PHY_PRECURSOR_LANE_1&#160;&#160;&#160;0x0250</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Controls the pre-cursor level. </p>

</div>
</div>
<a class="anchor" id="a8d13e1e98899a0d08dff3fe38f252f3a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_PHY_STATUS&#160;&#160;&#160;0x0280</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Current PHY status. </p>

</div>
</div>
<a class="anchor" id="a7d43076a9bf9d542f5ce46655c3f5ebe"></a>
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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_PHY_STATUS_ALL_LANES_READY_MASK&#160;&#160;&#160;0x00000013</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>All lanes are ready. </p>

</div>
</div>
<a class="anchor" id="a9085fff8bbafbfe31b3305dc8978e0c3"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XDPPSU_PHY_STATUS_GT_PLL_LOCK_MASK&#160;&#160;&#160;0x00000010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>GT PLL locked status. </p>

</div>
</div>
<a class="anchor" id="a0481f9e3c07f6d6586cb9b053a97a4b7"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XDPPSU_PHY_STATUS_RATE_CHANGE_LANE_0_DONE_MASK&#160;&#160;&#160;0x00000004</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Received PHYSTATUS pulse from GT after rate change request from lane 0. </p>

</div>
</div>
<a class="anchor" id="a87d2936b12e86306850adc2c5ddb44bc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_PHY_STATUS_RATE_CHANGE_LANE_1_DONE_MASK&#160;&#160;&#160;0x00000008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Received PHYSTATUS pulse from GT after rate change request from lane 1. </p>

</div>
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<a class="anchor" id="a0f0c53eed3bb612db95cead36ee12954"></a>
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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_PHY_STATUS_RESET_LANE_0_DONE_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Reset done for lane 0. </p>

</div>
</div>
<a class="anchor" id="acbc96ec2c0ce6b3659a90dedc4324b03"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_PHY_STATUS_RESET_LANE_1_DONE_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Reset done for lane 1. </p>

</div>
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<a class="anchor" id="ad4d20e2d6ab1c2d9d4cd8ef7e1f6e04a"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XDPPSU_PHY_TRANSMIT_PRBS7&#160;&#160;&#160;0x0230</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Enable pseudo random bit sequence 7 pattern transmission for link quality assessment. </p>

</div>
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<a class="anchor" id="a236d6b24b5cf2e0e8ac65a4079ae93bc"></a>
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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDpPsu_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;XDpPsu_In32((BaseAddress) + (RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This is a low-level function that reads from the specified register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset to be read from.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the specified register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xdppsu__hw_8h.html#a236d6b24b5cf2e0e8ac65a4079ae93bc" title="This is a low-level function that reads from the specified register. ">XDpPsu_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>

<p>Referenced by <a class="el" href="xdppsu__common__example_8h.html#a64d2267afa217a44aa3bf09bcd51e409">DpPsu_StartLink()</a>, <a class="el" href="xdppsu_8h.html#abe31bd9b101b094a40eff13ef032ea44">XDpPsu_EstablishLink()</a>, <a class="el" href="xdppsu__intr_8c.html#a940393f7b33c36e51ea69d4561630222">XDpPsu_HpdInterruptHandler()</a>, <a class="el" href="xdppsu_8h.html#a17608072027dcae9a885b07ad2c25690">XDpPsu_IicRead()</a>, <a class="el" href="xdppsu_8h.html#a2602de9c767cd981896326433a3c2570">XDpPsu_InitializeTx()</a>, <a class="el" href="xdppsu_8h.html#aee45a79c993e3bcad636dddf3121aeab">XDpPsu_IsConnected()</a>, <a class="el" href="xdppsu_8h.html#a6eec1f08aa677fac3467a9d34b54589c">XDpPsu_ResetPhy()</a>, and <a class="el" href="xdppsu__selftest_8c.html#a361b97262d5192f5f357fb4fb27b3ec8">XDpPsu_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="a6290aae7acf47770b47ca197d0a0c6c9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_REPLY_DATA_COUNT&#160;&#160;&#160;0x0148</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Total number of data bytes actually received during a transaction. </p>

</div>
</div>
<a class="anchor" id="aa9125d1e1b2dd161005e744f50514539"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_REPLY_STATUS&#160;&#160;&#160;0x014C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Reply status of most recent AUX transaction. </p>

</div>
</div>
<a class="anchor" id="a5451b49271e361e747472252d4bf19cd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_REPLY_STATUS_REPLY_ERROR_MASK&#160;&#160;&#160;0x00000008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Detected an error in the AUX reply of the most recent transaction. </p>

</div>
</div>
<a class="anchor" id="a0fcf6a885af08954316e8fa77914a437"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_REPLY_STATUS_REPLY_IN_PROGRESS_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX reply is currently being received. </p>

</div>
</div>
<a class="anchor" id="a147de67b6171acd49f0c14722980cf88"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_REPLY_STATUS_REPLY_RECEIVED_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX transaction is complete and a valid reply transaction received. </p>

</div>
</div>
<a class="anchor" id="a881e39fa5e38787ed558c988de819f24"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_REPLY_STATUS_REPLY_STATUS_STATE_MASK&#160;&#160;&#160;0x00000FF0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Internal AUX reply state machine status bits. </p>

</div>
</div>
<a class="anchor" id="a3989bff7e9babcb97ac85f2760bea47c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Shift bits for the internal AUX reply state machine status. </p>

</div>
</div>
<a class="anchor" id="a28186a7d8691e88a0b470365a4e6ccd7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK&#160;&#160;&#160;0x00000004</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX request is currently being transmitted. </p>

</div>
</div>
<a class="anchor" id="a6025e9ebba67eb43d4e7894386b0806e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_SCRAMBLING_DISABLE&#160;&#160;&#160;0x0014</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Disable scrambler and transmit all symbols. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a690be0eee00d0c06370f88fdfbfdfb75">XDpPsu_SetScrambler()</a>.</p>

</div>
</div>
<a class="anchor" id="a71f335fd19c1b8f3bc3eb9a3fbf4644c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_SOFT_RESET&#160;&#160;&#160;0x001C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Software reset. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a2602de9c767cd981896326433a3c2570">XDpPsu_InitializeTx()</a>.</p>

</div>
</div>
<a class="anchor" id="a3a7707ccbeb559d57c0def91f0f49c43"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_SOFT_RESET_EN&#160;&#160;&#160;0x1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Indicates that the soft reset has been set. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#a2602de9c767cd981896326433a3c2570">XDpPsu_InitializeTx()</a>.</p>

</div>
</div>
<a class="anchor" id="aa2d0f8311673ee64d8836b35d31c09ad"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_TRAINING_PATTERN_SET&#160;&#160;&#160;0x000C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Set the link training pattern. </p>

</div>
</div>
<a class="anchor" id="a8f2c84354e5bb55cd069cea5322ff051"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_TRAINING_PATTERN_SET_OFF&#160;&#160;&#160;0x0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Training off. </p>

<p>Referenced by <a class="el" href="xdppsu_8h.html#abe31bd9b101b094a40eff13ef032ea44">XDpPsu_EstablishLink()</a>.</p>

</div>
</div>
<a class="anchor" id="a9d807ffa394367098f9b64878158da17"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_TRAINING_PATTERN_SET_TP1&#160;&#160;&#160;0x1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Training pattern 1 used for clock recovery. </p>

</div>
</div>
<a class="anchor" id="a44d60c953f9bcf0e6354301c5d0e8915"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_TRAINING_PATTERN_SET_TP2&#160;&#160;&#160;0x2</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Training pattern 2 used for channel equalization. </p>

</div>
</div>
<a class="anchor" id="acf6992e1d3931bb1f6ceb82666b5d354"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_TRAINING_PATTERN_SET_TP3&#160;&#160;&#160;0x3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Training pattern 3 used for channel equalization for cores with DP v1.2. </p>

</div>
</div>
<a class="anchor" id="a842268c74f2d73c00df473e71fb54b86"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_TU_SIZE&#160;&#160;&#160;0x01B0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Size of a transfer unit in the framing logic. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>.</p>

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<a class="anchor" id="a72f3966bc5404d485e40130efefe701e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_TX_AUDIO_CHANNELS&#160;&#160;&#160;0x0304</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Used to input active channel count. </p>

</div>
</div>
<a class="anchor" id="a2a830ba69a1227e5e0c81723ac207564"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_TX_AUDIO_CONTROL&#160;&#160;&#160;0x0300</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Enables audio stream packets in main link and buffer control. </p>

</div>
</div>
<a class="anchor" id="acdaec86673f448a838cd31963d7368ff"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_TX_AUDIO_EXT_DATA&#160;&#160;&#160;0x0330</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Word formatted as per extension packet. </p>

</div>
</div>
<a class="anchor" id="a4a62dd1033e79b46709a6cecff92ab78"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_TX_AUDIO_INFO_DATA&#160;&#160;&#160;0x0308</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Word formatted as per CEA 861-C info frame. </p>

</div>
</div>
<a class="anchor" id="a4e35ebb4abdeb956bdb8d9612ea69be2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_TX_AUDIO_MAUD&#160;&#160;&#160;0x0328</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>M value of audio stream as computed by the DisplayPort TX core when audio and link clocks are synchronous. </p>

</div>
</div>
<a class="anchor" id="af176e2e67b35f97360402daad2386f9f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_TX_AUDIO_NAUD&#160;&#160;&#160;0x032C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>N value of audio stream as computed by the DisplayPort TX core when audio and link clocks are synchronous. </p>

</div>
</div>
<a class="anchor" id="a14ddf17f3094011de0f16a11d86bbc63"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_TX_PHY_POWER_DOWN&#160;&#160;&#160;0x0238</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Controls PHY power down. </p>

</div>
</div>
<a class="anchor" id="a6100fd7c2396d31135f5576668e244d3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_TX_USER_FIFO_OVERFLOW&#160;&#160;&#160;0x0110</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Indicates an overflow in user FIFO. </p>

</div>
</div>
<a class="anchor" id="a30a942297a72b501359f4818da8e5515"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_USER_DATA_COUNT_PER_LANE&#160;&#160;&#160;0x01BC</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Used to translate the number of pixels per line to the native internal 16-bit datapath. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>.</p>

</div>
</div>
<a class="anchor" id="aa9be13696d4f6db43e903d239a61dd2b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_USER_PIXEL_WIDTH&#160;&#160;&#160;0x01B8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Selects the width of the user data input port. </p>

<p>Referenced by <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>.</p>

</div>
</div>
<a class="anchor" id="a24ceb9ccb9922017c077c8ec72fd3ad2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_VERSION&#160;&#160;&#160;0x00F8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Core version. </p>

</div>
</div>
<a class="anchor" id="a5d53acb81f244f49bb023b24d11837e9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_VERSION_CORE_PATCH_MASK&#160;&#160;&#160;0x00000030</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Core patch details. </p>

</div>
</div>
<a class="anchor" id="a6101169897ad4c4cff60a1cd8d9feb12"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDPPSU_VERSION_CORE_PATCH_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Shift bits for core patch details. </p>

</div>
</div>
<a class="anchor" id="a6aa9d8689866ac3282305549d70fad0b"></a>
<div class="memitem">
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          <td class="memname">#define XDPPSU_VERSION_CORE_VER_MJR_MASK&#160;&#160;&#160;0x0000F000</td>
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<p>Core major version. </p>

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          <td class="memname">#define XDPPSU_VERSION_CORE_VER_MJR_SHIFT&#160;&#160;&#160;24</td>
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<p>Shift bits for core major version. </p>

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<a class="anchor" id="afe2062db881f2df560a2e899f09290b8"></a>
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          <td class="memname">#define XDPPSU_VERSION_CORE_VER_MNR_MASK&#160;&#160;&#160;0x00000F00</td>
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      </table>
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<p>Core minor version. </p>

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<a class="anchor" id="a0587f207575f813f9614bd249c0e4785"></a>
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          <td class="memname">#define XDPPSU_VERSION_CORE_VER_MNR_SHIFT&#160;&#160;&#160;16</td>
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<p>Shift bits for core minor version. </p>

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<a class="anchor" id="a774c413c2cffe51cae5c8156cf740afc"></a>
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          <td class="memname">#define XDPPSU_VERSION_CORE_VER_REV_MASK&#160;&#160;&#160;0x000000C0</td>
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      </table>
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<p>Core version revision. </p>

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<a class="anchor" id="ae46d9afaf4347d48ca7c12393b871dce"></a>
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          <td class="memname">#define XDPPSU_VERSION_CORE_VER_REV_SHIFT&#160;&#160;&#160;12</td>
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<p>Shift bits for core version revision. </p>

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          <td class="memname">#define XDPPSU_VERSION_INTER_REV_MASK&#160;&#160;&#160;0x0000000F</td>
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      </table>
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<p>Internal revision. </p>

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          <td class="memname">#define XDPPSU_VS_LEVEL_0&#160;&#160;&#160;0x3</td>
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<p>Voltage swing level 0. </p>

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<a class="anchor" id="a2b47f206d94602c469782d1ba28edec2"></a>
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          <td class="memname">#define XDPPSU_VS_LEVEL_1&#160;&#160;&#160;0x7</td>
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<p>Voltage swing level 1. </p>

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          <td class="memname">#define XDPPSU_VS_LEVEL_2&#160;&#160;&#160;0XB</td>
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<p>Voltage swing level 2. </p>

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<a class="anchor" id="a379d6347dbcc32330051ceef7ec181d4"></a>
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          <td class="memname">#define XDPPSU_VS_LEVEL_3&#160;&#160;&#160;0xF</td>
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<p>Voltage swing level 3. </p>

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          <td class="memname">#define XDPPSU_VS_LEVEL_OFFSET&#160;&#160;&#160;0x4</td>
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<p>Voltage swing compensation. </p>

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          <td class="memname">#define XDpPsu_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;XDpPsu_Out32((BaseAddress) + (RegOffset), (Data))</td>
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<p>This is a low-level function that writes to the specified register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset to write to. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit data to write to the specified register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xdppsu__hw_8h.html#a823328e4a95aa3ba27553603940a7ba8" title="This is a low-level function that writes to the specified register. ">XDpPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>

<p>Referenced by <a class="el" href="xdppsu_8h.html#ad113ed848850849d07fae7ce163a8a62">XDpPsu_EnableMainLink()</a>, <a class="el" href="xdppsu__intr_8c.html#a940393f7b33c36e51ea69d4561630222">XDpPsu_HpdInterruptHandler()</a>, <a class="el" href="xdppsu_8h.html#a2602de9c767cd981896326433a3c2570">XDpPsu_InitializeTx()</a>, <a class="el" href="xdppsu_8h.html#a6eec1f08aa677fac3467a9d34b54589c">XDpPsu_ResetPhy()</a>, <a class="el" href="xdppsu_8h.html#a7836168f290562156a24fb51762acde4">XDpPsu_SetDownspread()</a>, <a class="el" href="xdppsu_8h.html#a2ec5ae4af1f5232fc86116d457045997">XDpPsu_SetEnhancedFrameMode()</a>, <a class="el" href="xdppsu_8h.html#a868ca9bd2184707f3929e6f7e695cc93">XDpPsu_SetLaneCount()</a>, <a class="el" href="xdppsu_8h.html#a68384c6a808dff1f2e68e7611057a548">XDpPsu_SetLinkRate()</a>, <a class="el" href="xdppsu__spm_8c.html#a0ae04780a260564bbae1fd7c26155bd5">XDpPsu_SetMsaValues()</a>, and <a class="el" href="xdppsu_8h.html#a690be0eee00d0c06370f88fdfbfdfb75">XDpPsu_SetScrambler()</a>.</p>

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